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Making the Most of Hardware Formal Verification
June 28, 2010
Organized by IBM Research - Haifa


09:30 - Registration, light refreshments

09:50 - Welcome
Sivan Rabinovich, HRL Formal Verification group

10:00 - Formal Verification Essentials
Ziv Nevo, HRL Formal Verification group

In this opening talk, we will summarize what we covered in our last seminar, including:

  • Introduction to formal verification: basic uses and technology
  • Additional applications of the technology beyond functional verification
  • IBM experience with formal verification in Power7
  • Formal verification methodology
This is a good chance to learn more about this technology, which is becoming increasingly prevalent in the functional verification of hardware projects.

11:00 - Coffee Break

11:20 - Announcing RuleBase PE 2.07

We are proud to present the new version of RuleBase PE 2.07. This release introduces several new features. We will present:
  • Support for System Verilog designs and assertions - we extend our assertion language support to include also SVA
  • Assume synthesis - an easier way to describe your FV environment without the performance penalty
  • Other new features as time permits...
11:30 - Formal Verification Live Demo

We will hold a live demo of RuleBase PE that includes a walk through of the main features of the tool and the usage model. Methodology is an essential part of any formal verification project. We will demonstrate how your methodology can fit into the tool to support a productive and fast verification cycle.

12:30 - Coffee Break

12:30 - Formal Verification in Mellanox
Alon Webman, VP of Engineering, Switch Products, Mellanox Technologies

Mr. Alon Webman will discuss his company's use of formal verification during the last several years. The rest of the talk will be an open discussion, providing an opportunity to get first-hand information about the technology.

13:30 - Light Lunch

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