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Compiler and Architecture Seminar 2002

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Preliminary Program
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Compilers in HRL
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Program
Available in pdf 38KB

9:30 Arrival

9:45 Welcome
David Bernstein, Mgr. Systems and Software, IBM Haifa Research Lab

Session 1: Compilers

10:00 Design of a C Compiler for EZchip Net Processor,
Gil Timnat, EZchip (abstract)

10:30 Simple Inter-procedural Register Allocation in Compiler for NP,
Mostafa Hagog, IBM Haifa Research Lab (abstract , Presentation)

11:00 Compiler for a DSP Architecture,
Ayal Zaks, IBM Haifa Research Lab (abstract)

11:30 - 11:50 Coffee Break

Session 2: Architectures

11:50 Self-Stabilizing Microprocessor,
Yinnon Haviv, Ben-Gurion University (abstract , Presentation)

12:20 Banias Next Generation Mobile Processor,
Ronny Ronen, Intel (abstract)



13:00 - 14:00 Lunch

Keynote

14:00 Future Challenges in Computer System Design in the e-Business On Demand Era,
Kemal Ebcioglu, IBM T.J. Watson Research Center (abstract)

Session 3: Parallel Systems

15:00 Intrathreads Techniques for Parallelizing Sequential Code,
Alex Gontmakher, Technion (abstract)

15:30 A New Parallel and Fully Recursive Multifrontal Supernodal Sparse Cholesky,
Gil Shklarski, Tel-Aviv University (abstract , Presentation)

16:00 - 16:20 Coffee Break

Session 4: Memory Hierarchy

16:20 Post-Link Optimization Technology,
Gad Haber, IBM Haifa Research Lab (abstract , Presentation)

16:50 Fragmented Line Caches,
Bishara Shomar, Intel - Technion (abstract)

17:20 Concluding Remarks,
Michael Rodeh, Director, IBM Haifa Labs



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