|
Design Methodology for Low Power High Performance Semi Custom Processor Cores,"
Great Lakes Symposium on VLSI, April 2004. |
|
Reducing Instruction Fetch Energy with Backwards Branch Control Information and Buffering
International
Symposium on Low-Power Electronics and Design, Seoul, South Korea, August 2003. |
|
A New Look at Exploiting Data Parallelism in Embedded Systems
International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES '03), October, 2003. |
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Vectorizing for a SIMdD architecture
International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES '03), October, 2003. |
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A novel low-power high-performance digital signal processor for communications and media applications
Workshop on Stream and Media Processors, November 2002 |
|
eLite DSP: a low-power high-performance signal processor architecture
IBM Thomas J. Watson Research Center, August 2002. |
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Alternative methods for exploiting data parallelism
IBM Thomas J. Watson Research Center, November 2002. |
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"Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit
levels,"
International Symposium on Low-Power Electronics and Design, August 2002. |
|
"Low power integrated scan-retention mechanism,"
International Symposium on Low-Power Electronics and Design, August 2002. |
|
"Unified Architecture Level Energy-Efficiency Metric,"
Great Lakes Symposium on VLSI, April 2002 |
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