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DAISY:  Dynamically Architected Instruction Set from Yorktown


DAISY Demo and Tutorial

VLIW tree instruction

Daisy picture Daisy picture Daisy picture Daisy picture

The figure below depicts the scheduling of a PowerPC code fragment into VLIW instructions by DAISY. The VLIW instructions use a tree format. VLIW tree instructions permit multiple ALU operations as well as multiple conditional branches to be executed in a single VLIW instruction (cycle). To accomplish this, at the start of each the VLIW machine reads the set of condition code registers. These condition code registers determine which path through the VLIW instruction tree is to be taken. Only operations on the taken path are executed (at least conceptually). This is in some ways similar to predicated execution.

In this example, 11 PowerPC ops were scheduled into 2 VLIW instructions (two machine cycles) with the DAISY compilation algorithm.

PowerPC to VLIW translation example

Note:An OFFPAGE branch has a target beyond the page boundary. When executed, OFFPAGE branches check if the target is translated. If yes, then the translation is branched to. Otherwise the translator is branched to. There are 3 separate paths through the 11 PowerPC instructions of this example:

The DAISY scheduling algorithm maintains precise exceptions, even though it does aggressive re-ordering of code for achieving performance. Namely, when an exception occurs while executing the translated VLIW code, it is always possible to find a corresponding PowerPC instruction in the PowerPC code. For example, VLIW2: corresponds to the point in the PowerPC code just before sli. This is useful for achieving full architectural compatibility.

To see how the scheduling is done step-by-step in DAISY for this example, you can take a look at our interactive demo (130K GIF). Click here if your display is between 640x480 pixels and 820x700 pixels. Click here if it is larger than 820x700. Here is also an explanation of relevant DAISY compilation principles.


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