Project Overview

As the number of circuits per chip continues to increase, the importance of optimizing designs for manufacturability becomes increasingly important. This project addresses the measurement and optimization of manufacturability or yield of a design. Current efforts are directed toward measuring the yield impact of spot defects and determining how to modify layouts to reduce their impact. The approach uses Voronoi diagrams to subdivide the design into areas that enable fast, accurate, and deterministic yield calculations for the impact of spot defects that follow a given size distribution.

References:

1. "Critical Area Computation for Missing Material Defects in VLSI Circuits", E. Papadopoulou, IEEE Trans on CAD, May 2001
2. "L-infinity Voronoi Diagrams and Applications to VLSI Layout and Manufacturing", E. Papadopoulou and D. T. Lee, Int Symp on Algs and Comp,1998.
3. "Critical Area Computations via Voronoi Diagrams", E. Papadopoulou and D. T. Lee, IEEE Trans on CAD, April 1999
4. Patent: "Incremental Critical Area Computation for VLSI Yield Prediction", E. Papadopoulou and M. Lavin, issued March 2000