Analysis Of Delay And Coupled Noise

Static timing analysis is an efficient method to verify timing of a large VLSI chip. Several problems in this area include:

1. Cycle stealing- A long timing path may be achieved by shifting the clock edges at latches.
2. Incremental timing- When part of the design was modified, an incremental timer is needed to get fast timing report.
3. Simultaneous switching of input pins of a logic gate- For switching of two FETs in series, the delay is longer than that of single FET switching by as large as 20%, while switching of two FETs in parallel, the delay is shorter than a single FET switching by as large as 30-40%.
4. Signal bounding problem- When signals with different slews are propagated through a gate, we found several methods to define the bounding signal.
5. When long parallel wires are routed near to each other, the switching of two wires in the opposite directions produces a large coupling noise, and affects the delay through both nets. A new c effective method is implemented.
6. Sensitivities to manufacture variability, such as leff, threshold voltage, etc.