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A Tool for State-based Power Analysis for SoCs

Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. Given all variations in the power consumed by a core, a designer is forced to run the spreadsheets hundreds of times for all cores with different parameters in order to get a representative picture of the SoC power consumption under different operating scenarios. This is clearly very time consuming and error prone on the expected coverage. It is easy to overlook specific scenarios and fail to explore fully the power design space when running the spreadsheet analysis manually.

SPA encapsulates a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, SPA defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SoC. SPA is a tool for early formal analysis and exploration of the power design space for core-based SoCs. The key to this analysis is a new formal model for the different states in which the SoC can operate. Given the Power State Machine (PSM) for each core, SPA computes the power state machine for the whole SoC as the product of all individual PSMs for the cores. It combines the spreadsheet-like calculations with the PSM model for each core, and formally computes the product power state machine for the whole SoC. It then performs a symbolic simulation of the product PSM for all possible input combinations or for specific scenarios.

System Block Diagram Power Analysis

As an example, consider the simple system in the block diagram above. It contains an Ethernet subsystem (represented by the EMAC3 and MadMal8 cores), a PowerPC processor and a few other cores. SPA was used to compute the min/max power dissipated during a specific scenario of a packet being received by the Ethernet controller (EMAC3) and transmitted to the MAL (MadMal8) and onto Memory over the PLB using the Memory controller (HSMC). The components that are activated in turn during the simulation are: EMAC, EMAC_IO, MAL, PLB Arbiter, MC, CPU. The other components are left as don't cares, which means that they may stay idle or go to sleep. The simulation starts at the all idle state. It first activates the EMAC_IO and EMAC to receive a packet (cycle 2). Then the MAL becomes active and the EMAC\_IO may go to idle (cycle 3). In cycle 4, the MAL transfers the data to memory, thus activating the PLB arbiter and the Memory controller; while the EMAC and EMAC_IO may transition to idle state. The other cycles refer to similar transactions between the EMAC, MAL, PLB and Memory. Of special interest is cycle 7 where the CPU becomes Active to process a packet descriptor, causing a jump in power dissipation. The line connecting the dots inside each min/max bar correspond to the power dissipation for the cores involved in the packet receive process only. This allows us to see where within the min/max power is the power for a specific scenario.

Papers:
  1. R. A. Bergamaschi and Y. Jiang, "State-Based Power Analysis for Systems-on-Chip", in Proceedings of the 40th ACM/IEEE Design Automation Conference, ACM/IEEE, June 2003
Developers: Reinaldo Bergamaschi, IBM Research
Yunjian William Jiang, UC Berkeley
Contact: Reinaldo Bergamaschi, berga@us.ibm.com


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