The emerging System-on-a-Chip business is enabling the rapid design of nearly complete systems on a single chip. This capability is generating a flood of system performance questions: how many packets/sec can this router design handle? What is the memory bandwidth requires to support two simultaneous MPEG streams?

The diversity of application coupled with the ever diminishing time to market is creating the need for new tools to support rapid SoC design at a level of abstraction above the register-transfer level. We are exploring the development of a library of reusable performance models that correspond to the hardware cores in IBM's Core Connect library plus a facility to rapidly assemble these core models into a complete performance model for a new SoC design. The goal is to help SoC designers make hardware and software trade-offs without having to enter the detail design process. The figure above depicts our vision of the tool needed.