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IBM pioneered the research on power distribution analysis and developed a state-of-the-art full-chip power supply noise analysis tool NOVA [1,2] for high-performance VLSI design. By integrating the package model with the chip model, NOVA distinguishes itself to be one of the first and few tools in the industry which can simultaneously analyze resistive IR drop and inductive delta-I noise on a full-chip scale. Based on NOVA's complete and accurate analysis, chip designers can easily identify the hot spots, optimize decoupling capacitor placement, minimize power supply noise, preserve signal integrity, and improve circuit performance.

According to the semiconductor industry road map, the power supply voltage will continue to scale down in the next decade. With the noise margin less than a few hundred millivolts, the control of power supply noise will be critical in determining the performance and reliability of integrated circuits. As a major component of the IBM common power analysis methodology CPAM [3], NOVA has been used extensively to perform the critical analysis for a broad range of IBM microprocessors, including the S/390, AS/400, RS/6000, and PowerPC processors, and made significant contribution to the successful development of these product lines.

  1. Howard H. Chen and David D. Ling, "Power supply noise analysis methodology for deep submicron VLSI chip design," in Proceedings, 34th Design Automation Conference, June 1997, pp. 638-643.

  2. Howard H. Chen and J. Scott Neely, "Interconnect and circuit modeling techniques for full-chip power supply noise analysis," IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part B: Advanced Packaging, vol. 21, no. 3, pp. 209-215, August 1998.

  3. J. Scott Neely, Howard H. Chen, Steven G. Walker, James Venuto, and Thomas J. Bucelot, "CPAM: a common power analysis methodology for high-performance VLSI design," in Proceedings, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging, October 2000, pp. 303-306.

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