Project Overview

MASH (Migration Assistant Shape Handler) is a layout migration system that allows rapid construction of a design migration solution. It is developed jointly by IBM Research and IBM EDA and it is being supported by IBM EDA. It consists of several components:

• Layout optimization engine: uses state of the art layout optimization algorithms and a novel minimum perturbation formulation to map layouts from a source technology to a target technology.
• Ground rule engine: allows a very flexible description of all IBM ground rules.
• Shape manipulation software: MASH uses various shape manipulation software programs to prepare input data for the layout optimization engine.
• API for system integration: provides a set of APIs to facilitate integration with an existing design environment. The API set also allows rapid construction of customized design migration solutions. Examples include: scaling of leaf-cell images of structured dataflow macros, redistribution of global wires and resizing of devices. An example of a Leaf-Cell migration follows:

MASH is used heavily inside IBM to migrate designs from one generation of IBM technology to the next generation of IBM technology without sacrificing layout density. It is also used to migrate designs from third party's technologies to IBM technologies.

MASH has been used to migrate dataflow macros for IBM S/390 and PowerPC processors, SRAM/DRAM macros and standard-cell libraries for IBM ASIC. It has also been used to evaluate the density impact of new technologies such as Alternating Phase Shift Mask.

Publications

1. F.L. Heng, L. Liebmann, J. Lund, "Application of Automated Design Migration to Alternating Phase Shift Mask Design", 2001 International Symposium on Physical Design, pp. 38-43. ISPD01 Presentation: http://www.ispd.cc/presentations/4_1.pdf
2. Z. Chen and F.L. Heng, "A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement", The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1998, pp. 56-63.
3. F.L. Heng, Z. Chen and G. Tellez, "A VLSI Artwork Legalization Technique Based on a New Criteria of Minimum Layout Perturbation", 1997 International Symposium on Physical Design, pp. 116-121.