PROJECT OVERVIEW
Logic Synthesis
Deep submicron high performance design requires a novel approach to
logic synthesis. Gain-based synthesis uses a delay-centric approach to
logic optimization which naturally targets timing
optimization. Parametrizing logic gates with gain rather than size
also obfuscate the need for a pre-placement wire load model. The
inevitable futility of wire load models is the primary cause for
synthesis-placement iterations. A gain based synthesis methodology,
being intrinsically load independent, focuses on restructuring a
circuit towards a placement independent optimum. The critical paths in
the optimized circuit are the intrinsic critical paths which placement
must contend with. Therefore the resultant synthesized circuits a good
starting point for subsequent physical design.
The gain based methodology is incorporated into IBM’s premier
synthesis tool, BooleDozer. It has been deployed for synthesizing for
the S/390 high performance microprocessors with very beneficial
results.
Placement Driven Synthesis
As VLSI technology scales into the deep submicron regime, wire delays
become the dominant factor in delay optimization. Coupled with
conflicting optimization objectives such as delay, area and
wireabilty, the timing closure problem of complex ASICs is the modern
day Gordian knot. The archaic way of performing multiple synthesis-
placement iterations is unacceptable when time to market is the holy
grail of every ASICs vendor. The solution to turn around time
reduction is to integrate synthesis and placement into a single tool,
therefore replacing the synthesis-placement loop by a single pass.
The state of the art timing closure tool PDS is born of the
collaboration of IBM Research and IBM EDA. It is the result of
integrating BooleDozer with Cplace, an internal placement tool. It has
been deployed for the ASICs design centers as well as for S/390 design
teams. PDS has been used for design closure of the most challenging
ASIC designs from our foundry customers. It has a substantial impact
on reducing the turn around time within the ASIC design flow.
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