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Design Automation

Custom Layout and Optimization

Layout Generation

Layout Generation


Several methodologies exist for creating the layers of shapes that are implemented on silicon wafers in order to create integrated circuit chips. Three common approaches are standard cell, custom design, and layout migration. In a standard cell approach, library cells containing much of the layer information are placed and then routed which provides the remaining interconnect shapes. For custom design, special cells may be created and/or larger areas may be defined at the shapes level. In some cases, the shapes associated with cells, macros, or chips may be migrated from one technology to another by making only those changes necessary to satisfy the rules of the new technology. In each approach, the efficiency and accuracy of producing the shapes is important.

The Custom Layout and Optimization group develops physical layout tools and methodologies to decrease the design time and effort and to increase the performance and manufacturability of chips designed or manufactured by IBM. Several of these projects are shown below.

Layout Migration
Yield Calculations Using Voronoi Diagrams
Chip Power And Voltage Analysis
Analysis Of Delay And Coupled Noise
Chip Manufacturability Analysis
Array Logic & Verification

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