Leading-edge systems-on-chip (SoC) designs today are approaching 20 Million gates and 0.5 to 1 GHz operating frequency. To implement these systems, designers are increasingly relying on reuse of intellectual property (IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. In practice, however, assembling an SoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. A new tool called "Coral" is being developed by IBM Research and EDA to automate the design of SoCs using cores. Coral contains new algorithms and methodologies for SoC design using cores based on the concept of a synthesizable "virtual design". Coral increases the productivity by raising the level of abstraction in which SoCs are designed.

Coral's main characteristics are:

• A unique encapsulation of the structural and functional information of the cores in virtual representations and properties.

• A synthesizable virtual design representation which is a high-level abstraction of the SoC Core encapsulation and glueless interfaces which free the designer from having to create any interface logic Algorithms for mapping a virtual design into a real design with all interconnections and glue logic.

• Special configuration menus which allow the designer to specify parameters to the SoC at the virtual design level.

For more details, see the DAC2000 paper.