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Buffer Optimization

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Project Overview

BuffOpt is a computer-aided design tool that performs interconnect synthesis on nets that exhibit performance degradation after the inital layout of a design has been completed. It uses several innovative algorithms to fix electrical problems and optimize the timing characteristics of the nets. These algorithms may resize the net's source, insert repeater circuits, perform wire sizing and metal layer assignment, optimize with higher-order delay modeling, and/or automatically guide the net's detailed routing. These optimizations are all performed within the context of the existing physical design.

BuffOpt is a core component of the ASIC physical design methodology. It has been used on many IBM semi-custom designs and hundreds of ASIC parts. It is currently used for virtually all of IBM's ASIC designs. It is also used by external customers such as Cisco, Compaq, and NEC, to complete ASIC deisgn for the IBM foundry.


University Ties


Conference Presentations

  • "A Practical Methodology for Early Buffer and Wire Resource Allocation," C.J. Alpert, J. Hu, S. S. Sapatnekar, and P. Villarrubia, to be presented at the IEEE/ACM Design Automation Conference, June, 2001.

  • "Buffered Steiner Trees for Difficult Instances," C.J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, and A. J. Sullivan, to be presented at the International Symposium on Physical Design, April, 2001.

  • "Buffer Library Selection," C.J. Alpert, G. Gandham, J. L. Neves, S. T. Quay, Proceedings of the International Conference on Computer Design, Austin, TX, pp. 221-226, September, 2000.

  • "Buffer Insertion with Accurate Gate and Interconnect Delay Computation," C.J. Alpert, A. Devgan, S. T. Quay, Proceedings 36th ACM/IEEE Design Automation Conference, pp. 479-484, 1999.

  • "Is Wire Tapering Worthwhile?" C.J. Alpert, A. Devgan, S. T. Quay, Proceedings of the International Conference on Computer-Aided Design, pp. 430-435, 1999.

  • "Buffer Insertion for Noise and Delay Optimization," C.J. Alpert, A. Devgan, S. T. Quay, Proceedings of the 34th ACM/IEEE Design Automation Conference, pp. 362-367, 1999.

  • "Wire Segmenting for Improved Buffer Insertion," C.J. Alpert, A. Devgan, Proceedings 34th ACM/IEEE Design Automation Conference, pp. 588-593, 1997.


Journal Publications

  • "Steiner Tree Optimization for Buffers, Blockages, and Bays," C.J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay, and S. S. Sapatnekar, to appear in IEEE Transactions on Computer-Aided Design, April, 2001.

  • "Interconnect Synthesis without Wire Tapering," C.J. Alpert, A. Devgan, J. P. Fishburn, S. T. Quay, to appear in IEEE Transactions on Computer-Aided Design, January, 2001.

  • "Buffer Insertion for Noise and Delay Optimization," C.J. Alpert, A. Devgan, S. T. Quay, IEEE Transactions on Computer-Aided Design, 18(11), pp. 1633-1645, November, 1999.


Patents

  • "Optimum Buffer Placement for Noise Avoidance," C.J. Alpert, A. Devgan, S. T. Quay, US Patent US06117182, September, 2000.

  • "Method and System for Segmenting Wires Prior to Buffer Insertion," C.J. Alpert, A. Devgan, S. T. Quay, US Patent US06044209, March, 2000.


Group Members

  • Steve Quay, Gopal Gandham, Jiang Hu, Anirudh Devgan, Jose Neves, Charles Alpert.


Contact: Charles J. Alpert
IBM Austin Research Laboratory
11400 Burnet Road, MS 9460
Austin, TX 78660

alpert@austin.ibm.com


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