Verification Methodology For The Blue Gene Project

Project Overview

The basic building block for Blue Gene is a single chip that contains multiple processors and the communication logic that connects the processors on that chip with the processors on other chips. The chip itself is fabricated using currently available IBM ASIC technology. The logic for the chip is described in VHDL, using a design methodology that is supported by a variety of VLSI CAD tools, including simulation, synthesis, placement ,timing and test. Most of the tools have been developed by IBM engineers (e.g., Booledozer synthesis, Awan hardware accelerator, etc.). Of particular importance is the verification of the chip VHDL, and it requires close cooperation of the verification team with the developers of the architecture and the logic designers.

Reference: Blue Gene Web Page