Computer Science

Virtually all activity on most VLSI chips is controlled by the periodic “beat” of one or more global clock signals. Driving this signal to about 10⁵ places on a high-end microprocessor CPU typically consumes about ten percent of the chip power. If the period or “beat” is not perfectly constant (clock jitter) or if the signal does not arrive everywhere at the desired time (clock skew) the chip will not run as fast as it could. Reducing chip power has also become more important for everything from portable devices to high-end servers. Usually most power-saving techniques involve a performance penalty, but resonant clocking has the promise of both recycling energy (reducing power) and actually increasing performance.

The global clock signal is perhaps more timing critical than any other signal on the chip, but it is also very repetitive and predictable. Resonant clocking techniques take advantage of this predictability to design a network that wants to oscillate at the desired frequency.

Resonant clock distributions have been designed and fabricated in the past, but usually at quite slow frequencies using off-chip discrete inductors, or for very small areas using on-chip inductors. To achieve high frequencies, and low skew across a large clock domain, it was necessary to innovate ways of designing distributed but tightly coupled oscillators. Many distributed oscillators are needed to resonate a large clock domain at high frequency, but unless these oscillators are tightly coupled, they could easily oscillate with different phases meaning unacceptable skew.

There are three basic types of resonant clock networks that have been published so far:

-Traveling wave oscillators (providing constant amplitude but varying phase)
-Standing wave oscillators (providing constant phase but varying amplitude)
-Coupled LC oscillators (providing constant phase and constant amplitude)

As noted only the third class of resonant clock network provides both constant phase and constant amplitude everywhere on the network, and this is the class we have chosen to pursue.

These coupled LC oscillators also allow a relatively small incremental change in design style from the present non-resonant clock distribution methodology presently used by IBM high-end processor chips. The present methodology involves large clock grids driven by a number of small wiring trees (see fig. 1). By simply adding four carefully designed spiral inductors and four capacitors to each tree, this non-resonant network becomes a resonant clock distribution network (fig. 2).

Figure 1: Large clock grids driven by a number of small wiring trees

Figure 2: Resonant clock distribution network

In figure 2, the hanging ends of the spiral inductors are connected to relatively large on-chip capacitors (not shown) that provide a local Vdd/2 voltage for the clock grid to oscillate around.

Research to date has included three test-chips with resonant clock structure. The first test-chip was an aggressive attempt to modify a small part of a clock distribution to be resonant at about three gigahertz. The chip including the resonant section worked up to 4.6 GHz, but on-chip diagnostics was not included. Two further chips designed at Columbia University using less aggressive technology at about one gigahertz had more testing capabilities and were shown to reduce both power and jitter by approximately a factor of three.

The research has been a collaboration between Steven Chan and his advisor Ken Shepard at Columbia University and Phillip Restle at IBM Research.