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Resonant Clock Networks
A 4.6
GHz resonant global clock distribution network, Steven C. Chan,
Phillip J. Restle, Norman K. James, Robert L. Franch, IEEE ISSCC
Digest of Technical Papers, p341-343, February, 2004
Abstract
This resonant global clock distribution scheme
has the potential to reduce global clock power and clock jitter.
In this scheme, the global clock is distributed from a single synchronous
source to a set of clock sectors arrayed throughout the chip. Unique
to this approach is that the clock capacitance in each sector is
made resonant with a set of on-chip spiral inductors.
1.1 - 1.6GHz Distributed
Differential Oscillator Global Clock Network, Steven C. Chan, Kenneth
L. Shepard, Phillip J. Restle, IEEE ISSCC Digest of Technical Papers,
February, 2005 (in press)
Abstract
A distributed differential oscillator global clock network
using on-chip spiral inductors is designed in a 0.18um 1.8V CMOS
technology. The 2mm x 2mm resonant clock network has a tank Q of
4.3 and achieves more than an order of magnitude less jitter than
a conventional non-resonant tree-driven-grid global clock network
and uses almost three times less power.
Uniform-phase, Uniform-amplitude,
Resonant Load Global Clock Distributions, Steven C. Chan, Kenneth
L. Shepard, Phillip J. Restle, Journal of Solid-State Circuits (in
press).
Abstract
This paper presents a new approach to global clock distribution
in which traditional tree-driven grids are augmented with on-chip
spiral inductros to resonate the clock capacitance at the fundamental
frequency of the clock mode. In this wcheme, the energy of the fundamental
resonates betwen electric and magnetic forms, and the reduced admittance
of the clock network allows the clock drivers to be sized smaller.
The resulting improvements in jitter and power are presented using
measurment results from two test chips, one fabricated in a 90-nm
and the other in a .18-lm CMOS technology.
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