Computer Science

Leakage is power consumed by the circuit when it is off, and this problem has emerged as the most critical design challenge for current and future integrated circuits because it limits the frequency, yield and power of most of IBM’s leading designs. Traditionally, Complementary Metal-Oxide Semiconductor (CMOS) circuits have had little or no leakage power, but due to continued scaling of device dimensions, leakage power is now increasing exponentially with each technology generation (see Figure 1). It is expected to be the dominant part of total power by 65nm process technology node. To accurately analyze and reduce leakage power, IBM Research has initiated a comprehensive program -- Leakage Avoidance and Analysis (LAVA).

Figure 1. Leakage power (sub-threshold and gate) is increasing at an exponential rate and is growing much faster than dynamic (or switching) power.

Leakage is dependent on several design variables (see Figure 2) and has two key components: sub-threshold and gate leakage. Sub-threshold leakage is dependent on process variations, supply voltage and temperature, while gate leakage is dependent on gate oxide thickness. Both gate and sub-threshold leakage are dependent on circuit topologies and logic of the circuit. LAVA accurately analyzes leakage by modeling within-chip and chip-to-chip process variations, probability-driven static leakage estimation, and temperature and power supply co-analysis. LAVA is organized into three main components: LAVA-Chip for chip-level leakage estimation and planning; LAVA-macro for unit and macro-level analysis and optimization; and LAVA-mod for leakage characterization and modeling of standard cells and design building blocks.

Figure 2. Leakage is dependent on circuit topology, operating environment, input patterns and process variations.

 

Figure 3. Overview of the different components of Leakage Avoidance and Analysis (LAVA).

Reducing leakage has emerged as a key objective in current and future chip designs. Several leakage minimization techniques have been developed in LAVA to reduce the active leakage of the circuit. For instance, LAVA performs simultaneous Vt-assignment and sizing to reduce both the gate and sub-threshold leakage. Leakage can also be reduced by assigning the circuit to a low leakage state by controlling the input and latch outputs. While leakage varies exponentially across the process spread, adaptive circuit design is critical in managing leakage in sub-90nm design processes. And, adaptive control of power supply voltage and threshold voltage significantly reduce leakage, while also improving circuit performance and parametric yield.

Figure 4. Leakage analysis for an ASIC chip in LAVA, considering power supply and temperature variations across the chip.

Figure 5. Sample screen shots of the graphical interface to LAVA tools.