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R.
Rao, Anirudh Devgan, D. Blaauw, D. Sylvester, “Paramateric Yield
Estimation considering Leakage Variability,” ACM/IEEE Design Automation
Conference, June 2004.
Abstract
Leakage current has become a stringent constraint in modern processor
designs in addition to traditional constraints on frequency. Since leakage
current exhibits a strong inverse correlation with circuit delay, effective
parametric yield prediction must consider the dependence of leakage current
on frequency. In this paper, we present a new chip-level statistical method
to estimate the total leakage current in the presence of within-die and
die-to-die variability. We develop a closed-form expression for total
chip leakage that models the dependence of the leakage current distribution
on a number of process parameters. The model is based on the concept of
scaling factors to capture the effects of within-die variability. Using
this model, we then present an integrated approach to accurately estimate
the yield loss when both frequency and power limits are imposed on a design.
Our method demonstrates the importance of considering both these limiters
in calculating the yield of a lot.
H. Su, F. Liu, Anirudh
Devgan, E. Acar, S. Nassif, “Full-chip Leakage Estimation considering
Power Supply and Temperature Variations,” In Proceedings of IEEE
International Symposium on Low Power Electronics and Design, 2003.
Abstract
Leakage power is emerging as a key design challenge in current
and future CMOS designs. Since leakage is critically dependent on operating
temperature and power supply, we present a full chip leakage estimation
technique which accurately accounts for power supply and temperature variations.
State of the art techniques are used to compute the thermal and power
supply profile of the entire chip. Closed-form models are presented which
relate leakage to temperature and VDD variations. These models coupled
with the thermal and VDD profile are used to generate an accurate full
chip leakage estimation technique considering environmental variations.
The results of this approach are demonstrated on large-scale industrial
designs.
R. Rao, J. Burns,
Anirudh Devgan, R. Brown, “Efficient Techniques for Gate Leakage
Computation,” In Proceedings of IEEE International Symposium on
Low Power Electronics and Design, 2003.
Abstract
Gate leakage current is expected to be the dominant leakage component
in future technology generations. In this paper, we propose methods for
steady-state gate leakage estimation based on state characterization.
An efficient technique for pattern-dependent gate leakage estimation is
presented. Further, we propose the use of this technique for estimating
the average gate leakage of a circuit using pattern-independent probabilistic
analysis. Results on a large set of benchmark ISCAS circuits show an accuracy
within 5% of SPICE results with 500X to 50000X speed improvement.
Anirudh Devgan and
Chandra Kashyap, “Block-based Static Timing Analysis with Uncertainty,”
In proceedings of IEEE/ACM International Conference on Computer Aided
Design, 2003.
Abstract
Static timing analysis is a critical step in design of any digitalintegrated
circuit. Technology and design trends have ledto significant increase
in environmental and process variationswhich need to be incorporated in
static timing analysis.This paper presents a new, efficient and accurate
block-basedstatic timing analysis technique considering uncertainty.This
new method is more efficient as its modelsarrival times as cumulative
density functions (CDFs) anddelays as probability functions (PDFs). Computationallysimple
expression are presented for basic static timing operations.The techniques
are valid for any form of the probabilitydistribution, though the use
piecewise linear modelingof CDFs is highlighted in this paper. Reconvergent
fanoutsare handled using a new technique that avoids path tracing.Variable
accuracy timing analysis can be performed byvarying the modeling accuracy
of the piecewise linearmodel. Regular and statistical timing on different
parts ofthe circuit can be incorporated into a single timing analysisrun.
Accuracy and efficiency of the proposed method is demonstratedfor various
ISCAS benchmark circuits.
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