Overview

Interconnect design and optimization is increasingly important in VLSI chip design. One key interconnect network is the on-chip global clock distribution network that distributes the critical clock signal to every clocked circuit on the chip. A set of evolving strategies and tools has been developed at IBM Research to design this clock network and has been applied to the design of most IBM server microprocessors over the past few years. The tools developed include a low-skew maze router and a gradient-based wire-width optimizer, now used in many high-performance ASIC (Application Specific Integrated Circuit) chips. For large microprocessors above 500 MHz, a new strategy involving trees driving a single grid was developed, which required a new set of tools for the design and optimization of this strongly-connected network. As innovative interconnect analysis and simulation methods, such as IBMciao, are developed at Research, they are also being quickly applied to the clock distribution and other critical networks. IBMciao provides a complete fullwave solution to Maxwell's equations for complex 3D interconnect structures, and these simulation results are studied using 3D animations created by OpenDX, another IBM Research project. A number of interconnect animations will be shown, which help provide intuitive insight into the new phenomena occurring in multi-GHz on-chip interconnects.