Cell is a heterogeneous chip multiprocessor
consisting of a 64-bit Power core, augmented with 8 specialized
co-processors based on a novel single-instruction multiple-data
(SIMD) architecture called SPU (Synergistic Processor Unit), for
data intensive processing as is found in cryptography, media and
scientific applications. The system is integrated by a coherent
on-chip bus.
Based on the analysis of available die area,
cost and power budgets, and achievable performance, the best approach
to achieving the performance target was the exploitation of parallelism
through a high number of nodes on a chip multiprocessor. To further
reduce power, the team opted for a heterogeneous configuration
with a novel SIMD-centered architecture.
This configuration combines the flexibility of
an IBM Power core with the functionality and performance-optimized
SPU SIMD cores.
Cell Block Diagram
In this organization, the SPU accelerators operate
from a local storage which contains instruction and data for a
single SPU. This local storage is the only
memory directly addressable by the SPU.
Based on these decisions to share compute semantics,
data types, and virtual memory model, the SPUs synergistically exploit
and amplify the advantages when combined with the IBM
64-bit Power ArchitectureTM
to form the Cell Broadband Engine Architecture.
