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Project description
Innovation Matters!
The Cell story
Heterogeneous
Chip Multi-Processing
Synergistic Processor
Unit (SPU)
Scalar Layering
and Cell Compilation
Synergistic Memory Flow
Control (MFC)
Cell Programming
and Applications
Cell Systems
Cell Chip
Awards and Honors
Patents
Publications
IBM Cell Chips
Home Page
Cell Specification
More information

Michael Gschwind



The Cell project at IBM Research 
  Project description 


The Cell Chip

Cell Die Photo

Cell Die Photo

The first Cell implementations have shown industry-leadership frequency and performance. Some Cell statistics:

  • Observed clock speed: a wide range of operating frequencies are supported to optimize for power and yield;
  • Peak performance (single precision): > 256 GFlops
  • Peak performance (double precision): >26 GFlops
  • Local storage size per SPU: 256KB
  • Area: 221 mm˛
  • Technology 90nm SOI
  • Total number of transistors: 234M
 
  Related Project Pages 
arrow Innovation Matters! The Cell Story
arrow The original Cell press release
arrow A Cell compiler
arrow The IBM Cell BE Product Page
arrow STI Cell Processor @ IBM Venture Capital Group
arrow High-frequency microarchitecture
arrow Power-aware microarchitectures
arrow guTS

 
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