The Synergistic Memory Flow Controller integrates the Synergistic Processor Units in the Cell system architecture. The MFC uses the Power protection model and address translation model to include the Synergistic Processor Units in the Cell protection and address translation capabilities provided by the Power Architecture™ core.

The Synergistic Memory Flow Controller provides the SPU with data transfer and synchronization capabilities, and implements the SPU interface to the high-performance Element Interconnect Bus which serves as the transportation hub for the Cell Broadband Engine Architecture.

The Synergistic Memory Flow Controller also implements the communication interface between the SPE and PPE elements, and serves as a high-performance data transfer engine, which performs bulk data transfers between the Synergistic Local Storage and Cell system memory.

By offloading data transfer from compute elements onto dedicated data transfer engines, the architecture allows data processing and data transfer to proceed in parallel, and support advanced programming methods such as software pipelining and double buffering.

By providing the ability to perform high performance data transfer asynchronously and in parallel with data processing on the PPE and SPEs, the MFC is also a key to programmer productivity by eliminating the need to explicitly interleave data processing and transfer at the program level.