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ARL Distinguished Seminar Series

Distinguished Speaker: April

  • Jacob Abraham

    Jacob A. Abraham
    Professor of Electrical and Computer Engineering,
    Professor of Computer Sciences,
    University of Texas at Austin

     

    When: April 9, 2008 | 10:30am-12:00pm
    Host: Gi-Joon Nam

     

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"Research in Verification, Test and Fault Tolerance"

Abstract:
This talk will describe my research in the areas of verification, manufacturing test and application-level fault tolerance for embedded systems on a chip.  A problem common to these areas is to overcome the state-space explosion problem when analyzing large systems.  Techniques studied employ abstractions based on static analysis of the design description, which exploit the hierarchy in the design.  The abstractions can be generated efficiently, and the approach scales well with increasing design sizes.  Applications to verification of complex designs demonstrate that improvements of several orders of magnitude in time can be achieved compared with conventional approaches.  A new direction in at-speed test, called "native mode self-test" automatically maps test sequences for faults in embedded modules to processor instructions.  The processor can then be used to test other modules, including mixed-signal cores for analog and RF specifications.  On-chip sensors can be used to facilitate test of RF modules.  Chip measurements show that the approach can predict the specifications of the mixed-signal modules with high accuracy, enabling low-cost manufacturing test.  Finally, efficient techniques have been developed for detecting errors during operation, and some of them show promise in the area of security.

Bio:
Jacob A. Abraham is Professor of Electrical and Computer Engineering and Professor of Computer Sciences at the University of Texas at Austin. He is also the director of the Computer Engineering Research Center and holds a Cockrell Family Regents Chair in Engineering. He received his Ph.D. in Electrical Engineering and Computer Science from Stanford University in 1974. His research interests include VLSI design and test, formal verification, and fault-tolerant computing. He has published extensively and has been included in a list of the most cited researchers in the world. He has supervised more than 70 Ph.D. dissertations, and is particularly proud of the accomplishments of his students, many of whom occupy senior positions in academia and industry. He has been elected Fellow of the IEEE as well as Fellow of the ACM, and is the recipient of the 2005 IEEE Emanuel R. Piore Award.

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Distinguished Speaker: December

"Structured Wide-Area Programming"

Abstract:
Internet today provides a wide range of services associated with web sites; examples include getting a stock quote, making an airline reservation, compressing a file or inverting a matrix. Each service may be likened to a basic operation in a computer, the internet computer. An application is a program written over the basic services, i.e., an orchestration of the services. This research is directed toward designing, implementing and studying an appropriate model of orchestration that would allow us to develop wide-area applications succinctly.

Just as structured programming gave programmers effective tools to organize the control flow of sequential programs, our research introduces mechanisms to organize the communication, synchronization and coordination in programs that run on wide-area networks. We have developed a programming model, called Orc, for structured wide-area programming. Orc includes constructs to orchestrate the concurrent invocation of services to achieve a goal -- while managing time-outs, priorities, and failure of sites or communication. The talk will give an introduction to Orc, and some of the ongoing research on enhancing the model.

The Orc web page is at http://orc.csres.utexas.edu

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Distinguished Speaker: November

"Microelectronics- the Beginning of the End, or the End of the Beginning?"

Abstract:
Power dissipation in Si CMOS will reach crisis proportions if one simply follows Moore's law. We will discuss novel transistors that could potentially consume much less power. These were conceived under the auspices of the SRC NRI Southwest Academy of Nanoelectronics (SWAN), funded by IBM and other member companies. Specifically we will discuss the Bilayer pseudoSpin Field Effect Transistor (BiSFET). This is based on a concept called "pseudospin" that is analogous to the spin of a electron. Other electron wavefunction engineering and tunneling based transistors will also be discussed.

Bio:
Sanjay Banerjee is the Cockrell Family Regents Chair Professor of Electrical and Computer Engineering and Director, Microelectronics Research Center, at the University of Texas at Austin. He received his B.Tech from the Indian Institute of Technology, Kharagpur, and his M.S. and Ph.D. from the University of Illinois at Urbana-Champaign in 1979, 1981 and 1983 respectively, all in electrical engineering. As a Member of the Technical Staff, Corporate Research, Development and Engineering of Texas Instruments Incorporated from 1983-1987, he worked on polysilicon transistors and dynamic random access trench memory cells used by Texas Instruments in the world's first 4Megabit DRAM, for which he was co-recipient of the Best Paper Award, IEEE International Solid State Circuits Conference, 1986. He has been Assistant Professor (1987-90), Associate Professor (1990-93), and Professor (1993-) at The University of Texas at Austin. He has over 580 archival refereed publications/talks, 7 books/chapters, and 26 U.S. patents. He has supervised over 40 Ph.D. and 50 MS students. He received the Engineering Foundation Advisory Council Halliburton Award, 1991, the Texas Atomic Energy Fellowship (1990-1997), Cullen Professorship (1997-2001) and the NSF Presidential Young Investigator Award in 1988. His recent awards include the Distinguished Alumnus Award, IIT (2005), Industrial R&D 100 Award (with Singh in 2004), ECS Callinan Award, 2003, IEEE Millennium Medal, 2000 and SRC Inventor Recognition Award, 2000. He is a Fellow of IEEE, and was a Distinguished Lecturer for IEEE Electron Devices Society, and the General Chair of the IEEE Device Research Conference, 2002. He is currently active in the areas of ultra high vacuum and remote plasma-enhanced chemical vapor deposition for silicon-germanium-carbon heterostructure MOSFETs and nanostructures. He is also interested in the areas of ultra-shallow junction technology and semiconductor device modeling.

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Distinguished Speaker: October

"C++0x: An overview"

Abstract:
A good programming language is far more than a simple collection of features. My ideal is to provide a set of facilities that smoothly work together to support design and programming styles of a generality beyond my imagination. Here, I briefly outline rules of thumb (guidelines, principles), with examples, that are being applied in the design of C++0x. Then, I present the state of the standards process (we are aiming for C++09) and give two examples: concepts and generalized initialization. Since there are far more proposals than could be presented in an hour, I'll take questions. According to plan the complete specification will have been voted on October 20.

Bio:
http://www.research.att.com/~bs/bio.html

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Distinguished Speaker: September

"Machines Reasoning about Machines"

Abstract:
Computer hardware and software can be modeled precisely in mathematical logic. If expressed appropriately, these models can be executable. This allows them to be used as simulation engines or rapid prototypes. But because they are formal they can be manipulated by symbolic means: theorems can be proved about them, directly, with mechanical theorem provers. But how practical is this vision of machines reasoning about machines? In turns out that researchers in academia and industry are using mechanical theorem provers to prove important theorems about commercial microprocessor designs, including processors by AMD, Motorola, IBM, Rockwell-Collins and others. Some of these microprocessor models execute at 90% the speed of C and have had important functional properties verified. In addition, we are modeling the Java Virtual Machine and are proving theorems about JVM methods. I will describe these and other recent applications of an industrial-strength version of the Boyer-Moore theorem prover.

Biography:
J Strother Moore holds the Admiral B.R. Inman Centennial Chair in Computing Theory at the University of Texas at Austin. He is also chair of the department. He is the author of many books and papers on automated theorem proving and mechanical verification of computing systems. Along with Boyer he is a co-author of the Boyer-Moore theorem prover and the Boyer-Moore fast string searching algorithm. With Matt Kaufmann he is the co-author of the ACL2 theorem prover. Moore got his PhD from the University of Edinburgh in 1973 and his BS from MIT in 1970. Moore was a founder of Computational Logic, Inc., and served as its chief scientist for ten years. He and Bob Boyer were awarded the 1991 Current Prize in Automatic Theorem Proving by the American Mathematical Society. In 1999 they were awarded the Herbrand Award for their work in automatic theorem proving. Moore is a Fellow of both the American Association for Artificial Intelligence and the ACM and is a member of the NAE. Boyer, Moore, and Kaufmann were awarded the 2005 ACM Software Systems Award for the Boyer-Moore theorem prover.

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Distinguished Speaker: July

"Multicore Programming Models and their Implementation Challenges"

Abstract:
The computer industry is at a major inflection point in its hardware roadmap due to the end of a decades-long trend of exponentially increasing clock frequencies. It is widely agreed that spatial parallelism in the form of multiple power-efficient cores must be exploited to compensate for this lack of frequency scaling. Unlike previous generations of hardware evolution, this shift towards multicore and manycore computing will have a profound impact on software. These software challenges are further compounded by the need to enable parallelism in workloads and application domains that have traditionally not had to worry about multiprocessor parallelism in the past.

In this talk, we will focus on the programming problem for tightly coupled homogeneous and heterogeneous multicore processors. We use an extended subset of the X10 language as a foundational execution model to compare and contrast different homogeneous and heterogeneous multicore programming models including Cilk, OpenMP, Java Concurrency Utilities, .Net Task Parallel Extensions, Intel Thread Building Blocks, Intel Concurrent Collections, CUDA, and Cn. We discuss implementation challenges that must be overcome to support lightweight concurrency for mainstream applications on multicore systems. Finally, we present early experiences with the new Habanero Multicore Software Research project at Rice University (http://habanero.rice.edu) that encompasses work on programming models, compilers, runtimes, and concurrency libraries so as to enable portable software that can run unchanged on a range of homogeneous and heterogeneous multicore systems.

Biography:
Vivek Sarkar conducts research in programming languages, program analysis, compiler optimizations and virtual machines for parallel and high performance computer systems, and currently leads the Habanero Multicore Software Research project at Rice University (www.habanero.rice.edu). Prior to joining Rice, he was Senior Manager of Programming Technologies at IBM Research. His responsibilities at IBM included leading IBM's research efforts in programming model, tools, and productivity in the PERCS project during 2002- 2007 as part of the DARPA High Productivity Computing System program. His past projects include the X10 programming language, the Jikes Research Virtual Machine for the Java language, the ASTI optimizer used in IBM's XL Fortran product compilers, the PTRAN automatic parallelization system, and profile-directed partitioning and scheduling of Sisal programs. Vivek became a member of the IBM Academy of Technology in 1995, an ACM Distinguished Scientist in 2006, and the E.D. Butcher Professor of Computer Science at Rice University in 2007. He holds a B.Tech. degree from the Indian Institute of Technology, Kanpur, an M.S. degree from University of Wisconsin-Madison, and a Ph.D. from Stanford University. In 1997, he was on sabbatical as a visiting associate professor at MIT, where he was a founding member of the MIT RAW multicore project.

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Distinguished Speaker: June

  • Mary F. Wheeler

    Professor Mary F. Wheeler
    Director, Center for Subsurface Modeling
    Texas Institute for Computational and Applied Mathematics
    University of Texas at Austin

     

    When: June 20, 2008 | 10:30am-12:00pm
    Host: Gi-Joon Nam

     

"Computational Environments for Coupling Multiphase Flow, Transport, and Mechanics in Porous Media for Modeling Carbon Sequestration"

Abstract:
There is consensus in the scientific community that increased levels of greenhouse gases contribute to recent trends in global warming and dramatic changes in weather patterns. Geologic sequestration by injection of CO2 into deep brine aquifers and reservoirs represents one of the most promising approaches for reducing atmospheric CO2. The basis for this potential is the huge global storage capacity existing in geologic formations (primarily deep saline aquifers) and the availability and close proximity of potential injection sites to power generation plants. However, such injections pose significant technical issues in efforts to ensure safety, to minimize leakage probability on a time scale of hundreds or even thousands of years, and to gain public acceptance.

A key goal of our work is to produce a prototypical computational system to accurately predict the fate of injected CO2 in conditions governed by multiphase flow, rock mechanics, multi-component transport, thermodynamic phase behavior, chemical reactions within both the fluid and the rock, and the coupling of all these phenomena over multiple time and spatial scales. Even small leakage rates over long periods of time can unravel the positive effects of sequestration. This effort requires high accuracy in the physical models and their corresponding numerical approximations. For example, an error of one percent per year in a simulation may be of little concern when dealing with CO2 oil recovery flooding, but such an inaccuracy for sequestration will lead to significantly misleading results that could fail to produce any long-term predictive capability. It is important to note that very few parallel commercial and/or research software tools exist for simulating complex processes such as coupled multiphase flow with chemical transport and geomechanics.

In order to address this challenge a robust reservoir simulator comprised of coupled programs that together account for multicomponent, multiscale, multiphase flow and transport through porous media and through wells and that incorporate uncertainty and include robust solvers is required. The coupled programs must be able to treat different physical processes occurring simultaneously in different parts of the domain, and for computational accuracy and efficiency, should also accommodate multiple numerical schemes. In addition, this problem solving environment or framework must have parameter estimation and optimal control capabilities. We present a "wish list" for simulator capabilities as well as describe the methodology employed in the IPARS software being developed at The University of Texas at Austin.

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Distinguished Speaker: May

"At-Speed Test Considering Deep Submicron Effects"

Abstract:
Timing optimization has made the timing performance integrated circuits increasingly sensitive to small delay defects and process variation. Traditional path delay and transition fault test approaches are increasingly inadequate, leaving functional or system test as the only options that accurately correlate test speed to functional speed. In addition, crosstalk, power supply noise, and temperature effects during structural delay test are often much worse than in functional operation, resulting in delay tests rejecting good chips.

This talk will describe a set of models, algorithms and tools, including the CodSim fault simulator and CodGen automatic test pattern generator that generate the K longest paths through each gate/line (KLPG), and how the number of paths tested depends on process spatial correlation. This work includes a recently developed dynamic compaction algorithm the produces pattern counts competitive with transition fault tests. I will discuss the low-cost power supply noise models that have been developed and demonstrated to control noise during compaction. I will also describe early results with a pattern reordering algorithm that produces delay tests with near-constant power, so that the chip temperature rises linearly during test, and so can be easily characterized. Finally, I will discuss our approach to incorporating capacitive crosstalk in delay tests.

Biography:
Duncan M. Hank Walker is professor and graduate advisor in the Department of Computer Science at Texas A&M University. His primary research interest is integrated circuit test and diagnosis, with additional interests in yield modeling, statistical static timing, variation-tolerant design and computer architecture. He received a BS in engineering from Caltech and MS and PhD in computer science from Carnegie Mellon University. He has worked at Hughes Aircraft and Digital Equipment and spent two months at IBM Austin Research Laboratory in the summer of 1997.

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Distinguished Speaker: May

"Flexible Allocation and management of space in Storage Systems"

Abstract:
Current file systems allocate storage statically at the time of their creation. This results in many suboptimal scenarios, for example: (a) space on the disk is not allocated well across multiple file systems, (b) data is not organized well for typical access patterns. We propose Virtual Allocation for flexible storage allocation. Virtual allocation separates storage allocation from the file system. It employs an allocate-on-write strategy, which lets applications fit into the actual usage of storage space without regard to the configured file system size. This improves flexibility by allowing storage space to be shared across different file systems. We present the design of virtual allocation and an evaluation of it through benchmarks based on a prototype system on Linux.

We describe two applications of Virtual Allocation. We consider (1) the problem of balancing locality and load in networked storage systems with multiple storage devices (or bricks) and (2) the problem of data distribution in heterogeneous devices such as flash and disk drives. We employ virtual allocation in designing user-optimal data migration in networked storage systems and in matching file characteristics to device characteristics. We will present results from Linux-based prototypes.

Biography:
Narasimha Reddy is currently a professor in the department of Electrical and Computer Engineering at Texas A & M University. During 1990-95, he was a research staff member at IBM Almaden Reserch Center. Reddy's research interests are in storage systems, computer networks and multimedia systems. Reddy receiveda Ph.D. from Univeristy of Illinois in 1990. He received an NSF Career award in 1996. One of his papers has been cited "for one of the most influential papers from the 1st ACM Multimedia Conference".

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Contact Information

Contact: Gi-Joon Nam

IBM Austin Research Lab
Bldg 904, Floor 6, Room 6D-000
Austin, Texas