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Click each year to expand and collapse sections.
 2004
Computer Architecture
Design Automation
Physical Design
VLSI Design
Computer Architecture
“Cooperative Software-Hardware Power Management
for DRAM” by H. Huang, E. Van Hensbergen,
T. W. Keller, F. L. Rawson III, K. Shin. Submitted to
ASPLOS 2004.
“Supporting
Isolation for Fault and Power Management with Fully Virtualized
Memory Systems” by F. L. Rawson III.
IBM Research Techincal Report 2004, RC23069.
“MEMPOWER:
A Simple Memory Power Analysis Tool Set”
by F. L. Rawson III. IBM Reseach Techincal Report 2004,
RC23068.
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Design Automation
“A Fast Oracle for Interconnect Delay Prediction”
by C. J. Alpert, J. Hu, S. T. Quay, S. S. Sapatnekar, and
C. Sze. Submitted to ACM/IEEE Design Automation Conference
(DAC), 2004.
“Fast and Flexible Buffer Trees that Navigate
the Physical Layout Environment” by C. J.
Alpert, M. Hrkic, J. Hu, and S. T. Quay. Submitted to
ACM/IEEE Design Automation Conference (DAC), 2004.
“Placement Stability Metrics”
by C. J. Alpert, G.-J. Nam, P. G. Villarrubia, and M. Yildiz.
Submitted to ACM/IEEE Design Automation Conference (DAC),
2004.
“Analysis of Analytic Solvers and Reflow Methods
for Cell Placement” by C. J. Alpert, G.-J.
Nam, and P. G. Villarrubia. Submitted to ACM/IEEE Design
Automation Conference (DAC), 2004.
“Delay and Slew Metrics Made Simple”
by C. J. Alpert, C. Kashyap, F. Liu, and A. Devgan. Submitted
to IEEE Transactions on Computer-Aided Design (TCAD) 2004.
“PERI: A Technique for Extending Delay and
Slew Metrics for Ramp Inputs” by C. Kashyap,
C. J. Alpert, A. Devgan, and F. Liu. IEEE Transactions
on Computer-Aided Design (TCAD), April, 2004.
“A Delay Metric for RC Circuits Based on the
Weibull Distribution” by F. Liu, C. Kashyap,
and C. J. Alpert. IEEE Transactions on Computer-Aided
Design (TCAD), March 2004.
“A Place and Route Aware Buffered Steiner
Tree Construction” by J. Hu, C.-N. Sze, and
C. J. Alpert. IEEE/ACM Asia South Pacific Design Automation
Conference, January 2004.
“Complexity Analysis and Speedup Techniques
for Optimal Buffer Insertion with Minimum Cost”
by W. Shi, Z. Li, and C. J. Alpert. IEEE/ACM Asia South
Pacific Design Automation Conference, January 2004.
“Simultaneous Driver Sizing and Buffer Insertion
Using a Delay Penalty Estimation Technique”
by C. J. Alpert, C. N. Chu, G. Gandham, M. Hrkic, J. Hu,
C. Kashyap, and S. T. Quay. IEEE Transactions on Computer-Aided
Design (TCAD), January 2004, pp. 136-140.
“A Fast Oracle for Interconnect Delay Prediction”
by C. J. Alpert, J. Hu, S. T. Quay, S. S. Sapatnekar, and
C. Sze. ACM/IEEE Int'l. Workshop on Timing Issues in
the Specification and Synthesis of Digital Systems (TAU)
2004.
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Physical
Design
"A Comparative Study of Two Boolean Formulations
of FPGA Detailed Routing Constraints" by G.-J.
Nam, F. Aloul, K. Sakallah, R. Rutenbar. To appear in
IEEE Transactions on Computers.
“A Fast Algorithm for Identifying Good Buffer
Insertion Candidate Locations” by C. J. Alpert,
M. Hrkic, and S. T. Quay. Int'l Symposium on Physical
Design (ISPD) 2004.
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Top
VLSI
Design
"The
Recursive NanoBox Processor Grid: A Reliable System Architecture
for Unreliable Nanotechnology Devices"
by AJ KleinOsowski, K. KleinOsowski, D. J. Lilja, V. Rangarajan,
P. Ranganath. DSN 2004 - Int'l Conference on Dependable
Systems and Networks, IEEE Computer Society, Florence, Italy,
June 2004.
"Reducing Power Consumption in Mixed-Signal
Designs" by J.-A. Carballo. Proc. of the
Communications Design Conference, CDC 2004, San Fransisco,
CA, March 2004.
"Manufacturing-aware Design Methodologies for
Mixed-Signal Communication Circuits" by J.-A.
Carballo, S. Nassif. Proc. of SPIE, Design and Process
Integration Conference, Santa Clara, CA, Feb. 2004.
“Advanced
Waveform Models for Nanometer Regime”
by S. Nassif, E. Acar. ACM/IEEE International Workshop
on Timing Issues in the Specification and Synthesis of Digital
Systems, February 2-3, 2004.
"The
Nanobox Project: Exploring Fabrics of Self-Correcting Logic
Blocks for High Defect Rate Molecular Device Technology"
by AJ KleinOsowski, D. Lilja. Symposium on VLSI, IEEE
Computer Society, Lafayette, LA, Feb. 2004.
"Analysis and Optimization of Enhanced MTCMOS
Scheme" by R. Rao, J. Burns, R. Brown. The
Int'l Conference on VLSI Design (VLSI Design 2004), Mumbai,
India, January 5-9, 2004, to be published.
"Mixed-Signal Design as System-Circuit Co-Design"
by J.-A. Carballo, R. Singh. Electronic Engineering
Times (EETimes).
"Two-Dimensional Position Detection System
with MEMS Accelerometer for MOUSE Application"
by G.-J. Nam, S. Lee, J. Chae, H. Kim, A. Drake. Submitted
to IEEE Transactions on VLSI Systems.
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Top
2003
Algorithms & Threory
Design Automation
Low Power
Operating Systems
Physical Design
Power Analysis and Modeling
Reliable Systems/Autonomic Computing
VLSI Design
Algorithms
& Theory
"Process Variation
Aware Clock Tree Routing" by B. Lu, J.
Hu, G. Ellis, H. Su. Proc. of the 2003 International
Symposium on Physical Design, Monterey, CA, April 2003.
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Top
Design
Automation
"A
Heuristic to Determine Low Leakage Sleep State Vectors for
CMOS Combinational Circuits" by R. M.
Rao, F. Liu, J. L. Burns, R. B. Brown. Int'l Conference
on Computer Aided Design (ICCAD'03), San Jose, CA, pp. 689-692,
November 9-13, 2003.
"Full-chip Leakage Estimation Considering On-chip
Environmental and Process Variations" by A.
Devgan, E. Acar, H. Su, Y. Liu and S. Nassif. Submitted
to International Conference on Computer Aided Design 2003,
Nov 2003.
"A Methodology
for the Simultaneous Design of Supply and Signal Networks"
by H. Su, J. Hu, S. Sapatnekar, S. Nassif. TCAD, November
2003.
“Optimal Path Routing in Single and Multiple
Clock Domain Systems” by S. Hassoun, and
C. J. Alpert. IEEE Transactions on Computer-Aided Design
(TCAD), November 2003, pp. 1580-1587.
“Free Space Management for Cut-Based Placement”
by C. J. Alpert, G. Nam, and P. G. Villarrubia. IEEE
Transactions on Computer-Aided Design (TCAD), October 2003,
pp. 1343-1353.
“Delay and Slew Metrics Using The Lognormal
Distribution” by C. J. Alpert, F. Liu, C.
Kashyap, and A. Devgan. ACM/IEEE Design Automation Conference
(DAC), June 2003, pp. 382-385.
Download Slides
"Integrated Clock
and Power Network Analysis" by W. Kai,
H. Su, S. Nassif. DAC 2003, Anaheim, CA, June 2003.
“A Practical Methodology for Early Buffer
and Wire Resource Allocation” by C. J. Alpert,
J. Hu, S. S. Sapatnekar, and P. G. Villarrubia. IEEE
Transactions on Computer-Aided Design (TCAD), May 2003,
pp. 573-583.
"A Practical Methodology for Early Buffer and
Wire Resource Allocation" by C. J. Alpert,
J. Hu, S. S. Sapatnekar, and P. G. Villarrubia. IEEE
Transactions on Computer-Aided Design, 22(5), May 2003.
"Buffer Insertion with Adaptive Blockage Avoidance"
by J. Hu, C. J. Alpert, S. T. Quay, and G. Gandham. IEEE
Transactions on Computer-Aided Design, 22(4), April 2003.
"Optimal Decoupling
Capacitor Sizing and Placement for Standard Cell Layout
Designs" by H. Su, S. Sapatnekar, S. Nassif.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, Vol - 22 No - 4 Pages - 428-36, April
2003.
"Full Chip
Leakage Estimation Considering Power Supply and Temperature
Variations" by H. Su, F. Liu, A. Devgan,
E. Acar, S. Nassif. ISLPED 2003.
"Analysis and
Optimization of Power Grids" by S. Sapatnekar,
H. Su. IEEE Design and Test Magazine 2003.
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Top
Low Power
"Energy
Management for Commercial Servers" C.
Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler,
T. Keller. IEEE Computer, Dec, 2003.
"Evaluation
of Dynamic-Threshold Logic for Low-Power VLSI Design in
0.13µm PD-SOI" by Alan J. Drake,
Kevin J. Nowka, Richard B. Brown. IFIP VLSI-SoC International
Conference 2003, Darmstadt, Germany, pp. 363-368, December
1-3, 2003.
"The Design
and Application of the PowerPC 405LP Energy-Efficient System-on-a-chip"
by K. Nowka, G. Carpenter, and B. Brock. IBM Journal
of Research and Development, vol. 47, no. 5/6, pp. 631-640,
Sept.-Nov., 2003.
View
this issue of the Journal
"On
the Performance and Use of Dense Servers"
by W. Felter, T. Keller, M.D. Kistler, C. Lefurgy, K. Rajamani,
R. Rajamony, F. Rawson, B. Smith, and E. van Hensbergen.
IBM Journal of Research and Development, vol. 47, no.
5/6, pp. 671-688, Sept.-Nov., 2003.
"Dynamic
Power Management for Embedded Systems"
by B. Brock and K. Rajamani. Proc. of the IEEE Int'l
SOC Conference (SOCC 2003), Portland, Oregon, Sept. 2003.
"Dynamic Power
Management for Embedded Systems" by H.
Blanchard, B. Brock, M. Locke, M. Orvek, R. Paulsen and
K. Rajamani. Whitepaper.
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Top
Operating Systems
"Console Over Ethernet" by
M. Kistler, E. Van Hensbergen, F. Rawson. Proc. of FREENIX,
June 2003.
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Top
Physical
Design
"Effective Free Space Management for Cut-Based
Placement Via Analytical Constraint Generation"
by C. Alpert, G.-J. Nam, P. Villarrubia. IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems.
"Closed
Form Expressions for Extending Step Delay and Slew Metrics
to Ramp Inputs" by C. Kashyap, C. Alpert,
Y. Liu, A. Devgan. Proc. of the 2003 Int'l Symposium
on Physical Design (ISPD 2003), Monterey, California, April
2003, pp. 24-29.
"Porosity
Aware Buffered Steiner Tree Construction"
by C. Alpert, J. Hu, S. Quay, R. Gandham. Proc. of the
Int'l Symposium on Physical Design (ISPD 2003), Monterey,
California, April 2003, pp. 158-165.
“Buffer Insertion with Adaptive Blockage Avoidance”
by J. Hu, C. J. Alpert, S. T. Quay, and G. Gandham. IEEE
Transactions on Computer-Aided Design (TCAD), April 2003,
pp. 492-497.
“Minimum Buffered Routing with Bounded Capacitive
Load for Slew Rate and Reliability Control” by
C. J. Alpert, A. B. Kahng, B. Liu, I. Mandoiu, and A. Zelikovsky.
IEEE Transactions on Computer-Aided Design (TCAD), 22(3),
March 2003, pp. 241-253.
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Top
Power Analysis
and Modeling
"Design
and Validation of a Performance and Power Simulator for
PowerPC Systems" by H. Shafi, P. Bohrer,
J. Phelan, C. Rusu, J. Peterson. The IBM Journal of
Research and Development, Vol 47, No. 5/6, Nov 2003.
"Full Chip Leakage Estimation Considering Power
Supply and Temperature" by H. Su, F. Liu,
A. Devgan, E. Acar, S. Nassif. Int'l Symposium on Low
Power Electronics and Design 2003, (ISLPED 2003), Seoul,
Korea, Aug 2003.
"Power
Grid Reduction Based on Algebraic Multigrid Principles"
by H. Su, E. Acar and S. Nassif. Proc. of the 40th IEEE/ACM
Design Automation Conference 2003 (DAC 2003), Anaheim, California,
June 2003.
"Optimal
Shielding/Spacing Metrics For Low Power Design"
by R. Arunachalam, E. Acar and S. Nassif. Proc. of IEEE
Annual Symposium on VLSI (ISVLSI), Tampa, Florida, Feb 2003.
"Predicting Short
Circuit Power From Timing Models" by E.
Acar, R. Arunachalam and S. Nassif. Proc. of the Asia
Pacific Design Automation Conference 2003, (ASPDAC), Kitakyushu,
Japan, Jan 2003.
"Leakage
and Leakage Sensitivity Computation for Combinational Circuits"
by E. Acar, A. Devgan, R. Rao,Y. Liu, H. Su, S. Nassif,
J. Burns. Proc. of the Int'l Symposium on Low Power
Electronics and Design 2003, (ISLPED 2003), Feb 2003.
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Top
Reliable
Systems/Autonomic Computing
"Raptor: Integrating Checkpoints and Thread
Migration for Cluster Management" by H. Shafi,
E. Speight (Cornell University), and J. Bennett (University
of Colorado). The 22nd Int'l Symposium on Reliable
Distributed Systems (SRDS '03), Florence, Italy, October,
2003.
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Top
VLSI Design
"Designing with Hard Power Constraints in
90nm and Beyond" by J.-A. Carballo. Electronic
Engineering Times.
"Signal Integrity – Buckle Down, It’s
Here to Stay" by J.-A. Carballo, R. Singh.
Electronic Engineering Times.
“Analysis
of the Impact of Gate-Body Signal Phase on DTMOS Inverters
in 0.13µm PD-SOI” by A. Drake,
N. Zamdmer, K. Nowka, and R. Brown. IEEE International
SOI Conference, Newport Beach, CA, pp. 99-100, September
29-October 2, 2003.
“Resonant Clocking
using Distributed Parasitic Capacitance”
by A. Drake, K. Nowka, T. Nguyen, J. Burns, and R. Brown.
Custom Integrated Circuits Conference (CICC), San Jose,
CA, pp. 647-650, September 21-24, 2003.
"Circuit
Techniques for Gate and Sub-Threshold Leakage Minimization
in Future CMOS Technologies" by R. Rao,
J. Burns, and R. Brown. European Solid-State Circuits
Conference (ESSCIRC 2003), Lisbon, Portugal, September 16-18,
2003, to be published.
"Efficient
Techniques for Gate Leakage Estimation"
by R. M. Rao, J. Burns, A. Devgan, and R. B. Brown. Int'l
Symposium on Low Power Electronics and Design (ISLPED'03),
Seoul, Korea, pp. 100-103, August 25-27, 2003.
"Value-based Management of Design Reuse"
by J.-A. Carballo. Cost and Performance in Integrated
Circuit Creation, SPIE Proceedings, vol. 5043, 2003, p.
72-81, Santa Clara, CA, Feb. 2003.
"A Semi-Custom Voltage-Island Technique and
its Application to High-Speed Serial Links"
by J.-A. Carballo, S.-M. Yoo, I. Vo, J. L. Burns. Int'l
Symposium on Low Power Electronics and Design, ACM SIGDA
and IEEE Circuits and Systems Society, Santa Clara, CA,
Feb. 2003.
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Top
2002
“PERI: A Technique for Extending
Delay and Slew Metrics for Ramp Inputs”
by C. Kashyap, C. J. Alpert, A. Devgan, and F. Liu.
ACM/IEEE Int'l. Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU), December 2002, pp.
57-62.
“Free Space Management for Cut-Based
Placement” by C. J. Alpert, G.-J. Nam, and
P. G. Villarrubia. ACM/IEEE International Conference
on Computer-Aided Design (ICCAD), November 2002, pp. 746-751.
“WED: A Delay Metric for RC
Circuits Based on the Weibull Distribution”
by F. Liu, C. Kashyap, and C. J. Alpert. ACM/IEEE International
Conference on Computer-Aided Design (ICCAD), November 2002,
pp. 620-624.
Download Slides
“Optimal Path Routing in Single
and Multiple Clock Domain Systems” by
S. Hassoun, C. J. Alpert, and M. Thiagarajan. ACM/IEEE
International Conference on Computer-Aided Design (ICCAD),
November 2002, pp. 247-253.
Download Slides
"A Linear Centric Simulation Framework for
Parameter Fluctuations" by E. Acar, L. T.
Pileggi, S. Nassif. Proc. of Design Automation
Conference of Europe 2002 (DACE), March 2002.
"Time-Domain Simulation of Variational Interconnect
Models" by E. Acar, S. Nassif, Y. Liu and
L. Pileggi. Proc. of Int'l Symposium on Quality
Electronic Design 2002 (ISQED), March 2002.
“Buffered Steiner Trees for
Difficult Instances” by C. J. Alpert, G.
Gandham, M. hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu,
S. T. Quay, S. S. Sapatnekar, A. J. Sullivan. IEEE Transactions
on Computer-Aided Design (TCAD), 21(1), January 2002, pp.
3-14.
Low
Power
"Super-Dense Servers: An Energy-efficient
Approach to Large-Scale Server Clusters"
by C. Lefurgy. Presentation for Graduate Seminar,
Department of Computer Science, Texas A&M University,
November 2002.
Download
Slides
"The
Case for Power Management in Web Servers"
by P. Bohrer, E. N. Elnozahy, T. Keller, M. Kistler, C.
Lefurgy, C. McDowell, and R. Rajamony. Power Aware
Computing, Editors R. Graybill and R. Melhem, Klewer Academic
Publishers, 2002.
"Energy-Efficient
Server Clusters" by E. N. Elnozahy,
M. Kistler, and R. Rajamony. Proc. of the Second
Workshop on Power Aware Computing Systems, Feb. 2, 2002
(held in conjunction with HPCA-2002).
"Free Space Management for Cut-based
Placement Via Analytical Constraint Generation"
by C. Alpert, G.-J. Nam, P. Villarrubia. International
Conference on Computer-Aided Design 2002.
"Hybrid
Routing for FPGAs By Integrating Boolean Satisfiability
with Geometric Search" by G.-J. Nam, K.
Sakallah, R. Rutenbar. Int'l Conference on Field Programmable
Logic and Applications (FPL), Lecture Notes in Computer
Science, vol. 2438, 2002, p. 360-9, Montpellier, France,
Sept. 2002.
"A New FPGA Detailed Routing
Approach Via Search-Based Boolean Satisfiability" by
G.-J. Nam, K. Sakallah, R. Rutenbar. IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems,
Vol - 21 No - 6 Pages - 674-84, June 2002.
“Buffer Insertion with Adaptive
Blockage Avoidance” by J. Hu, C. J. Alpert,
S. T. Quay, and G. Gandham. Int'l Symposium on Physical
Design (ISPD), April 2002, pp. 92-97.
“Simultaneous Driver Sizing
and Buffer Insertion Using a Delay Penalty Estimation Technique”
by C. J. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu,
C. Kashyap, and S. T. Quay. Int'l Symposium on Physical
Design (ISPD), April 2002, pp. 104-109.
VLSI Design
“A
32-bit PowerPC system-on-a-chip with support for dynamic
voltage scaling and dynamic frequency scaling”
by K. Nowka, G. Carpenter, E. MacDonald, H. Ngo, B. Brock,
K. Ishii, T. Nguyen, J. Burns. IEEE Journal of Solid-State
Circuits, Volume: 33, Issue: 11, Nov. 2002, pp. 1600 -1608.
"Impact of Technology in Power-Grid Induced
Noise" by J.-A. Carballo, S. Nassif. PATMOS
2002 (Power and Timing Modeling, Optimization and Simulation),
Seville, Sept. 2002.
“A 16-Bit by 16-Bit MAC Design Using Fast
5:3 Compressor Cells” by O. Kwon, K. Nowka,
E. Swartzlander, Jr. The Journal of VLSI Signal Processing,
v. 31, no. 2, Jun 2002, pp. 77-89.
“Probability-Driven Routing
in a Datapath Environment” by S.
Raman, S. S. Sapatnekar, and C. J. Alpert. Integration:
The VLSI Journal, 31(2), May 2002, pp. 159-182.
"Reuse and Quality Enhancement
via Computation and Distribution of Component Derivative
Rewards" by J.-A. Carballo, W. Belluomini,
R. Montoye, D. Cohn. Electronic Design Processes Workshop
2002.
"Specification
and Implementation of Dynamic Web Site Benchmarks"
by C. Amza, A. Chanda, E. Cecchet, A.. Cox, S. Elnikety,
R. Gil, J. Marguerite, K. Rajamani, and W. Zwaenepoel.
IEEE Workshop on Workload Characterization (WWC5),
November 25, 2002.
"On-chip
MRAM as a High-Bandwidth, Low-Latency Replacement for
DRAM Physical Memory" by R. Desikan,
C. Lefurgy, S. Keckler and D. Burger. Technical Report
TR-02-47, Department of Computer Sciences, The University
of Texas at Austin, September 27, 2002.
Download
Slides
"Singularity Network Processor Advanced
Reference Platform" by E. Van Hensbergen,
B. Brock. IBM Research Technical Report, RC22631,
2002.
“Issues in High Frequency Processor Design”
by K. Nowka. The Computer Engineering Handbook, ed.
V. Oklobdzija, CRC Press, 2002.
“A
0.9V to 1.95V dynamic voltage-scalable and frequency-scalable
32b powerPC processor” by K. Nowka,
G. Carpenter, E. Mac Donald, H. Ngo, B. Brock, K. Ishii,
T. Nguyen. J. Burns. IEEE International Solid-State
Circuits Conference, Digest of Technical Papers. 2002,
v1. pp. 340-341, v2. pp. 272-273, 503.
"A Reward-based Economic Model for Component
Reuse" by J.-A. Carballo, W. Belluomini,
R. Montoye, D. Cohn. International Workshop on Reuse
Economics 2002, (part of Int'l Conf. on Software Reuse).
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