The Rivina 64-bit PowerPC processor is a fully compliant implementation
of the 64-bit PowerPC (TM) instruction set architecture. The design
uses the same "delayed-reset" dynamic circuit family as the previously
completed "guTS" integer processor. Control logic is realized entirely
in programmable logic arrays (PLAs), followed by a single level of
static or dynamic circuits. The 4kB single cycle caches used in the
integer prototype were replaced with two-cycle 64kB caches.
Unlike typical GHz processor with pipelines that range from 14-20
stages, the Rivina pipeline contains just 6 stages, and many operations
are completed in a single cycle. A full address translation unit was
added, as well as a dual-precision IEEE compliant floating-point unit.
Clock distribution was also vastly improved, with total clock skew
less than 16ps across the chip. The new fixed-point adder architecture
incorporated in this design is also used to speed up IBM's current
commercial i- and p- series e-servers.
The processor contains many additional micro-architectural innovations
such as instruction dependency prediction, and novel implementations
of data cache set prediction, a history file mechanism, and innovations
in the organization of the floating-point unit. The processor contains
19 million transistors, and was built in IBM's 0.22 micron CMOS process
using copper interconnect. The processor dissipates 112 Watts at 1.15
GHz.
The design was completed at an expense of less than twenty researchers
over a period of about two years.
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