Dynamic
Power Management for the IBM PowerPC 405LP
The IBM
PowerPC 405LP is the product of a collaboration between IBM
Microelectronics and the IBM Austin Research Laboratory, and
ARL is leading the effort to exploit the processor's capability
for low-latency dynamic voltage and frequency scaling.
Blazer
This embedded DRAM
macro is designed as a DRAM cache for a future gigahertz microprocessor
system.
Client-Perceived
Response Times on the WWW From
a user’s perspective, the response time is the time elapsed
from when a request is initiated at a client to the time that
the response is fully loaded by the client.
guTS
The IBM Gigahertz unit
Test Site (GUTS) completed early in 1997 contains a series of
experiments in high-frequency design, including the world's
first CMOS processor to reach 1GHz operation.
NUMA
Austin researchers
have demonstrated a new method for building a large scale server
based on Non-Uniform Memory Access (NUMA) technology with key
differentiators.
Rivina
The Rivina 64-bit PowerPC
processor prototype is a fully compliant implementation of the
64-bit PowerPC(TM) instruction set architecture.
SimOS-PPC
SimOS supports user-developed
packages for data and instruction cache simulation, the execution
profiling of all code, as well as providing a practical performance
and functional debugging environment for operating systems.
Super Dense Servers IBM Austin researchers developed the Super
Dense Server hardware as well as software which solves crucial
system management and performance problems inherent in blades.
High-Performance
Microprocessors IBM
Research is currently investigating how to better design and
manufacture high performance microprocessors.
