Recent advances in processor design techniques
have led to the development of systems that support very dynamic power
management strategies based on voltage and frequency scaling. Since
CPU power consumption typically decreases with the cube of voltage
while frequencies typically scale linearly with voltage, significant
opportunities exist for tuning the power-performance trade-off to
the needs of the application. An example is the recently announced
IBM PowerPC 405LP embedded processor, the product of a collaboration
between IBM Microelectronics and the IBM Austin Research Laboratory.
The 405LP was specifically designed for battery operated portable
systems, and supports aggressive power management strategies based
on low-latency dynamic voltage and frequency scaling. The 405LP scales
frequencies with a latency of a few microseconds, voltages with latencies
measured in tens of microseconds, and unlike competing implementations,
performs these operations without disrupting system operations during
the scaling events. The IBM Austin Research Laboratory,
IBM Linux Technology Center and MontaVista Software have initiated
a joint project to develop a dynamic power management framework
for Linux that enables the advanced features of the 405LP and other
members of the emerging class of processors supporting dynamic scaling.
This work has produced a whitepaper describing our approach to dynamic
power management, and a prototype Linux implementation of the proposed
framework for the 405LP.
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