This embedded DRAM macro is designed as a DRAM cache for a future
gigahertz micro-processor system from a logic-based DRAM technology.
The most notable feature of this macro is its ability to run synchronously
with a gigahertz CPU clock in a fully pipelined fashion. It is designed
to operate with a 1-GHz clock signal at 85 C, nominal process parameters,
and a 10% degraded VDD. The design is fully pipelined and synchronous
with 16 independent subarrays. With 1kB wide I/O and a 1-GHz clock,
the maximum data rate becomes 1 Tera bit per second. The address access
time is 3.7 ns, four cycles with a 1-GHz clock. The subarray cycle
time is 12 ns.
Presented at:
IEEE 2000 International Solid-State Circuits Conference
Published in:
IEEE Journal of Solid-State Circuits,
November 2000
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