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Publications

2008

  1. Para-virtualizing More Than Just Devices, Eric Van Hensbergen, First Workshop on I/O Virtualization, USENIX, San Diego, CA, December 2008.
  2. Handbook of Algorithms for Physical Design Automation, Edited by Charles J Alpert, Dinesh Mehta, Sachin Sapatnekar, November 11, 2008.
  3. Software Transactional Memory: Why is it Only a Research Toy?, Calin Cascaval, Colin Blundell, Maged Michael, Harold W. Cain, Peng Wu, Stefanie Chiras, and Siddhartha Chatterjee, Communications of the ACM, November 2008, Vol. 51, No. 11 and ACM Queue, August 2008.
  4. Detecting DMA Race Conditions in Cell/B.E. Applications with the IBM Full System Simulator, Michael D. Kistler, Daniel Brokenshire, Workshop on Design, Architecture and Simulation of Chip Multi-Processors, Cuomo, Italy, November 2008.
  5. Integrating MRAM as NUCA Caches in CMP Using 3D Stacking Technologies, Guangyu Sun, Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Jian Li, MICRO 2008 - The 41st Annual IEEE/ACM International Symposium on Microarchitecture, November 2008.
  6. Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency, Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, and Zhichun Zhu, To appear in Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy, November 8-12, 2008.
  7. Using Test Data to Improve IC Quality and Yield, Anne E. Gattiker, ICCAD -- Intl Conf on Computer Aided Design, San Jose, CA, November 2008.
  8. A Polynomial Time Approximation Scheme For Timing Constrained Minimum Cost Layer Assignment, Shiyan Hu, Zhuo Li, Charles Alpert, Proceedings of International Conference on Computer-Aided Design, November 2008.
  9. On-chip jitter and oscilloscope circuits using an asynchronous sample clock, Jeremy D. Schaub, Fadi H. Gebara, Tuyet Yen Nguyen, Ivan Vo, Jarom Pena, Joy Dhruva, ESSCIRC, Edinburgh, Scotland, October 2008.
  10. Nonlinear Circuit Solver with Linear Interconnect Load, Albert E. Ruehli, Jerry D. Hayes, Electrical Performance of Electronic Packaging Digest, San Jose, CA, October 2008.
  11. Unraveling Variability for Process/Product Improvement, Anne E. Gattiker, Proceedings of IEEE International Test Conference, Santa Clara, CA, October 2008.
  12. Stable High-Density FD/SOI SRAM with Selective Back-Gate Bias Using Dual Buried Oxide, Keunwoo Kim, Jente B. Kuang, Fadi H. Gebara, Hung C. Ngo, Ching-Te Chuang, Kevin Nowka, 2008 IEEE International SOI Conference, October 2008.
  13. Variability and Power Management in sub-100nm SOI Technology for Reliable High Performance Systems, Michael Rosenfield, Kerry Bernstein, Jeffrey Burns, Koushik Das, Fadi H. Gebara, Shih-Hsien Lo, Kevin Nowka, Rahul M. Rao, 2008 IEEE International SOI Conference, October 2008.
  14. Memory Access Scheduling Schemes for Systems with Multi-Core Processors, Hongzhong Zheng, Jiang Lin, Zhao Zhang, and Zhichun Zhu, In Proceedings of the 2008 International Conference on Parallel Processing (ICPP-08), Partland, Oregon, September 8-12, 2008.
  15. Characterization and Design for Variability and Reliability, Kevin Nowka, Sani R. Nassif, Kanak Agarwal, Custom Integrated Circuits Conference, San Jose, September 2008.
  16. Process Variability at the 65nm node and Beyond, Sani R. Nassif, Custom Integrated Circuits Conference, San Jose, September 2008.
  17. Root-Finding Methods for Assessing SRAM Stability in the Presence of Random Dopant Fluctuations, Rouwaida N. Kanj, Zhuo Li, Rajiv V. Joshi, Ying Liu, Sani R. Nassif, Transactions on semiconductor manufacturing, September 2008 (Invited extended version on special issue of ISQED).
  18. Getting to Productive Exaflop Systems, Ram Rajamony, Clusters and Computational Grids for Scientific Computing, Flat Rock, North Carolina, September 14-17, 2008
  19. Performance Scalability of Decoupled Software Pipelining, Ram Rangan, Neil Vachharajani, Guilherme Ottoni, and David I. August, ACM Transactions on Architecture and Code Optimization (TACO), Volume 5, Number 2, August 2008.
  20. Programming Massively Parallel Processors: CAD Examples, Damir Jamsek, 45th Design Automation Conference (DAC), Anaheim, CA, August 2008.
  21. An on-chip dual supply charge pump system for 45nm eDRAM, Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Yen Nguyen, Jeremy D. Schaub, Kevin Nowka, Gary D. Carpenter, Donald Plass, Erik Nelson, Ivan Vo, ESSCIRC - European Solid-State Circuit Conference, Edinburgh, UK, August 2008.
  22. SRAM Methodology for Yield and Power Efficiency: Per-Element Selectable Supplies and Memory Reconfiguration Schemes, Rouwaida N. Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Sani R. Nassif, Ying Zhou, W. Shi, International Symposium on Low power designs (ISLPD08), Bangalore, India, August 2008.
  23. Autonomic Multi-Agent Management of Power and Performance in Data Centers, Rajarshi Das, Jeffry O. Kephart, Charles Lefurgy, Gerald Tesauro, David W. Levine, and Hoi Chan, The 7th International Conference on Autonomous Agents and Multiagent Systems (AAMAS), 2008.
  24. A One MB Cache Subsystem Prototype with 2GHz Embedded DRAMs in 45nm SOI CMOS, William R. Reohr, Hillery Hunter, Jente B. Kuang, Proceedings 2008 Symposia on VLSI Technology and Circuits, IEEE Solid-State Circuits Society, June 2008.
  25. A High Performance 2.4 Mb L1 and L2 Cache Compatible 45 nm SRM with Yield Improvement Capabilities, Rajiv V. Joshi, R Houle, D Rodko, P Patel, W Houtt, Robert L. Franch, Y Chan, D Plass, S Wilson, S Wu, Rouwaida N. Kanj, Proceedings of 2008 IEEE Symposium on VLSI Circuits, pp 208-9, June 2008.
  26. Software Thermal Management of DRAM Memory for Multicore Systems, Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David and Zhao Zhang, In Proceedings of the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), Annapolis, Maryland, June 2-6, 2008.
  27. Dynamic Measurement of Critical Path Timing, Alan J. Drake, Robert M. Senger, Gary D. Carpenter, Norman James, Harmander Deogun, ICICDT 2008-International Conference on IC Design and Techonology, Grenoble, France, June 2008.
  28. Performance Optimized Design For Parametric Reliability, Ramyanshu Datta, Jacob Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin Nowka, Journal of Electronic Testing-Theory and Applications, Vol: 24, No: 1-3, Pages: 129-141, June 2008.
  29. Optimal Timing Driven Cloning with Linear Delay Model, Zhuo Li, David A. Papa, Charles Alpert, Chin Ngai Sze, Ying Zhou, Weiping Shi, DAC 2008 - 45th Design Automation Conference, June 2008.
  30. Pyramids: The Computational Geometry-based Approach for Timing-Driven Placement, Tao Luo, David A. Papa, Zhuo Li, Charles Alpert, DAC 2008 - 45th Design Automation Conference, June 2008.
  31. RATCHET: Discrete Optimization for Incremental, Timing-driven Physical-synthesis, Michael D. Moffitt, David A. Papa, Zhuo Li, Charles Alpert, DAC 2008 - 45th Design Automation Conference, June 2008.
  32. Path Smoothing Via Discrete Optimization, Michael D. Moffitt, Davis A. Papa, Zhuo Li, Charles Alpert, Proceedings of 2008 45th ACM/IEEE Design Automation Conference, pp. 724-7, June 2008.
  33. A framework for end-to-end simulation of high-performance computing systems and its application to PERCS design, Jian Li and Wolfgang E. Denzel, In IBM Academy of Technology - Performance Engineering 'Best Practice' Topical Conference, Southbury, CT, June 2008.
  34. An On-Chip Word Line Dual Supply System for 45nm PD SOI eDRAM, Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Kevin Nowka, Tuyet Yen Nguyen, Transactions VLSI, May 2008
  35. Variability in Nanometer CMOS: Impact, Analysis and Minimization, Dennis Sylvester, Kanak Agarwal, Saumil Shah, Integration-The VLSI Journal, Vol: 41, No: 3, Pages: 319-339, May 2008
  36. Accelerating Computing with the Cell Broadband Engine Processor, Catherine H. Crawford, Paul Henning, Michael Kistler, Cornell Wright, ACM Computing Frontiers, May 2008
  37. Efficient Transient Analysis of Power Grids with On-Chip Inductances, Chenggang Xu, Sani R. Nassif, Ying Liu, Raju Balasurbramanian, Erich Schanzenbach, IEEE/ACM GLSVLSI 2008, Orlando, FL, May 2008.
  38. Case Study: CFI-enabled Application Development Leveraging Community Resource, Xin Zhou, Ying Liu, Hui Su, Xin Zhang, 2008 International Conference on Service Science, Beijing, China, April 2008.
  39. Stress Aware Layout Optimization, Joshi Vivek, Dennis Sylvester, Blaauw David, Kanak B. Agarwal, ISPD 2008 - International Symposium on Physical Design, Portland, OR, April 2008.
  40. Spice: Speculative Parallel Iteration Chunk Execution, Easwaran Raman, Neil Vachharajani, Ram Rangan, and David I. August, Proceedings of the 2008 International Symposium on Code Generation and Optimization (CGO), April 2008.
  41. Multi-bit Upsets in 65nm SOI SRAM, Ethan H. Cannon, Michael S. Gordon, David F. Heidel, AJ Kleinosowski, Phil Oldiges, Kenneth P. Rodbell, Henry H. K. Tang, International Reliability Physics Symposium, April 2008.
  42. The Coming of Age of (Academic) Global Routing. Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov. In Proceedings of the 2008 International Symposium on Physical Design (ISPD-2008) April 2008 INVITED PAPER
  43. RUMBLE: An Incremental, Timing-driven, Physical-synthesis Optimization Algorithm. David A. Papa, Tao Luo, Michael D. Moffitt, C. N. Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov. In Proceedings of the 2008 International Symposium on Physical Design (ISPD-2008) April 2008
  44. The Impact of Aging Effects and Manufacturing Variation on SRAM Soft-Error Rate, Ethan Cannon, AJ KleinOsowski, Rouwaida N. Kanj, Daniel D Reinhardt, Rajiv V. Joshi, IEEE Transactions on Device and Materials Reliability, Vol: 8 No: 1 Pages: 145-152, March 2008.
  45. Compiler and Runtime Techniques for Software Transactional Memory Optimization, Peng Wu, Maged M. Michael, Christoph Von Praun, Takuya Nakaike, Rajesh Bordawekar, Harold W. Cain, Gheorghe Cascaval, Siddhartha Chatterjee, Stefanie R. Chiras, Rui Hou, Mark F. Mergen, Xiaowei Shen, Hua Yong Wang, Kun Wang, Michael Spear, Concurrency and Computation: Practice and Experience, March 2008.
  46. A Design Model for Random Process Variability, Victoria Wang, Markovic Dejan, Kanak B. Agarwal, Sani R. Nassif, Kevin Nowka, ISQED, March 2008.
  47. Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM design Yield, Rouwaida N. Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif, Proceedings of ISQED, March 2008.
  48. A Root-Finding Method for Assessing SRAM Stability, Rouwaida N. Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif, Proceedings of ISQED, March 2008.
  49. Fast Interconnect Synthesis with Layer Assignment, Zhuo Li, Charles Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia, Proceedings of 2008 International Symposium on Physical Design, March 2008.
  50. Rapid Characterization of Parametric Distributions Using a Multi-Meter, J Hayes, Kanak Agarwal, Sani R. Nassif, Proceedings of 2008 IEEE Conference on Microelectronic Test Structures, pp.17-20, March 2008.
  51. The Impact of Aging Effects and Manufacturing Variation on SRAM Soft Error Rate, Ethan Cannon, AJ Kleinosowski, Rouwaida N. Kanj, Daniel Reinhardt, and Rajiv V. Joshi, IEEE Transactions on Device and Materials Reliability, March 2008.
  52. Bridging the gap between abstract RTL and bit-level designs, A. K. Martin, ETAPS 2008 Satilite Workshop on Designing Correct Circuits, Budapest, Hungary, March 2008
  53. A framework for end-to-end simulation of high-performance computing systems, Wolfgang Denzel, Jian Li, Peter Walker and Yuho Jin, In Intl. Conf. on Simulation Tools and Techniques for Communications, Networks and Systems (SimuTools), Mar. 2008. (Opening Session)
  54. Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs, Rouwaida Kanj, Rajiv Joshi, Jayakumaran Sivagnaname, JB Kuang, Dhruva Acharyya, Tuyet Nguyen and Sani Nassif, Accepted for publication in IEEE Trans. on Semiconductor Manufacturing, Feb. 2008. INVITED PAPER
  55. MaizeRouter: Engineering an Effective Global Router. Michael D. Moffitt. In Proceedings of the 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008) January 2008
  56. Holistic Aggregate Resource Environment; Charles Forsyth, Jim McKie, Ron Minnich and Eric Van Hensbergen. To be printed in the ACM Operating Systems Review; January 2008.
  57. Specialized Execution Environments; Dilma Da Silva, et. al. To be printed in the ACM Operating Systems Review; January 2008.
  58. On the synergy between Exploration and Maturity in Sytems Work at IBM Research; Muli Ben-Yehuda and Eric Van Hensbergen. To be printed in the ACM Operating Systems Review; January 2008.
  59. Power Grid Analysis Benchmarks, Sani R. Nassif, Proceedings of 13th Asia and South Pacific Design Automation Conference ASP-DAC, January 2008.
  60. Technology Modeling and Characterization Beyond the 45nm Node, Sani R. Nassif, Proceedings of 13th Asia and South Pacific Design Automation Conference ASP-DAC, January 2008.
  61. A Temperature Aware Power Estimation Methodology, Madhu Saravana Sibi Govindan, Stephen W. Keckler, Sani R. Nassif, Emrah Acar, ASPDAC, January 2008.
  62. Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies, Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka, IEEE Trans VLSI, January 2008.
  63. The ISPD Global Routing Benchmark Suite, G.-J. Nam, C. N. Sze, M. Yildiz, ACM International Symposium on Physical Design (ISPD), pp. 156-159, 2008.
  64. On-chip Jitter and Oscilloscope Circuits Using an Asynchronous Sample Clock, J. D. Schaub, F. H. Gebara, T. Y. Nguyen, I. Vo, J. Peña, D. J. Acharyya, 2008 ESSCIRC, pp. 126-129.

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