"IBM
Systems Power Management "
Brad McCredie, IBM
Fellow
Bio:
Brad received his BS, MS, and PhD in electrical and
computer engineering from the University of Illinois
in ’85, ’87 and ’91
respectively. His primary interests were electromagnetic modeling and
simulation. Brad then joined IBM and continued his work in packaging
in Poughkeepsie focused on IBM’s mainframe systems. In ’96
he moved to IBM Austin and began working on POWER based systems. Today
Brad is an IBM Fellow and is currently focused on POWER6 and POWER7 system
design.
"Seizing
Energy Efficiency Opportunities to Address Energy
Supply and Climate Challenges" Andrew Fanara, USEPA, Energy Star Product
Specifications Team Leader
Abstract:
Our energy supply and environmental landscape are undergoing
substantial
fundamental change. Citizens and corporations from around
the globe
are coming to this realization. Myriad near and long
term solutions,
are being offered as the debate in policy circles intensifies.
Strategies to improve the energy efficiency of various
facets of our
energy economy are increasingly proving to be inexpensive,
clean and
quick to implement. Pursuing such strategies, as positive
market
interventions, can help businesses seize competitive
opportunities and
reduce risk associated with their use of energy.
Bio:
Andrew Fanara manages the ENERGY STAR® Product Specifications
Development Team. ENERGY STAR is part of the U.S. Environmental
Protection Agency’s Climate Protection Partnership
Division. The ENERGY STAR Program is intended to help
businesses and individuals protect the environment by
identifying products with superior energy efficiency
and water savings.
Mr. Fanara’s team is responsible for writing product
specifications and for teaming with manufacturers to
encourage the design, manufacture, and sale of products
that meet them.
To date, more than 40 product categories have been created
for the residential and commercial sectors. Over 1.5
billion ENERGY STAR products have been sold in the US,
and in 2005, these products will realize electricity
savings in excess of $6.5 billion.
Mr. Fanara’s team also manages the program’s
national energy model which is used to track energy consumption,
savings and market penetration data for ENERGY STAR products
sold in the US. Lastly, Mr. Fanara is responsible for
managing the implementation of a product compliance testing
verification initiative and for managing policy coordination
with countries using ENERGY STAR in their markets. This
includes Japan, Australia, New Zealand, Taiwan, Canada,
China, and the European Union.
He is a graduate of the University of Wisconsin - Madison
and has worked for the EPA for more than 10 years.
"Power
and Energy Efficient Design by System Co-optimization" Shekhar Borkar, Intel Fellow, Director,
Microprocessor Technology Lab
Abstract:
Moore's Law will continue for years to come, providing
billions of transistors; however, power, energy,
variability, and reliability will be the barriers.
Performance at any cost will not be an option in
the future; VLSI systems will have to emphasize performance
delivered in a given power envelope, with complexity
limited by energy efficiency, variability and reliability.
This talk will discuss potential solutions in process
technology, circuits, and microarchitectures to exploit
future gigascale integration capacity. This will
not be easy; chips, software, and platforms must
be co-designed and optimized for power and energy.
The talk conclude with recommendations to VLSI system
designers.
Bio:
Shekhar Borkar graduated with MS in Physics from University
of Bombay, MSEE from University of Notre Dame in 1981,
and joined Intel Corporation. He worked on the 8051
family of microcontrollers, the iWarp multicomputer
project, and subsequently on Intel's supercomputers.
He is an Intel Fellow and director of Microprocessor
Research. His research interests are high performance
and low power digital circuits, and high-speed signaling.
Shekhar is an adjunct faculty member at Oregon Graduate
Institute, and teaches VLSI design.
"Power
Aware On-Chip Networks"
Vijaykrishna Narayanan, Associate Professor, Computer
Science and Engineering Department., Pennsylvania
State University
Abstract:
The advent of multi-core architectures has marked the
beginning
of a gradual shift in design methodology, from centralized
monolithic
implementations to distributed communication-centric
designs.
Consequently, power expended in the interconnect fabric
has become a key
focus. In this talk, I will present several microarchitectural
techniques which reduce the power expended in on-chip
routers, without
adversely affecting performance. Specifically, I will
present an
optimized buffer architecture, and a decomposable router
structure which
breaks the switch into two smaller, distinct and independent
modules. In
addition to microarchitectural improvements, we will
also tackle the
issue from a higher-level perspective. Reliability
concerns necessitate
the inclusion of retransmission and error correcting
schemes in modern
communication architectures. I will highlight the tradeoff
between
reliability safeguards and power consumption. Finally,
I will conclude
by showing influence of 3D chips on on-chip communication
fabrics
Bio:
Vijaykrishnan Narayanan is an Associate Professor
of Computer
Science and Engineering at The Pennsylvania State University.
His
research interests include power aware architectures,
robust system
design, embedded systems and nanoarchitectures. He
is the Editor-in-Chief
of the ACM Journal on Emerging Technologies in Computing
Systems and an
Associate Editor of the IEEE Transactions on CAD and
IEEE Transactions
on VLSI.
“Power
Management Technology for Portable Devices”
Kevin Scoones, Distinguished
Member of Technical Staff, Texas Instruments
Abstract:
Portable devices are becoming increasingly
powerful and computation-intensive posing severe problems
for equipment manufacturers and thus power supply designers.
After the application and equipment designers have
completed their system partitioning and optimization,
the power supply designers are still left with a significant
contribution to make. This talk will discuss some of
the challenges and the technology used to meet them.
Bio:
Kevin Scoones joined Texas Instruments in the
U.K. in 1989 after graduating from Nottingham University
with a BEng in Electronic Engineering. In 1991 he moved
to Germany and has worked on power management devices
for the automotive, mobile phone and portable power
catalogue markets. He currently leads a team designing
integrated power management units for mobile devices
in TI’s High Performance Analogue division. He
is a Distinguished Member of the Technical Staff.
"Reliability:
The Next Frontier for Power-Efficient Design"
Sarita Adve, Professor, Dept. of Computer Science, University of Illinois, Urbana-Champaign
Abstract:
With continued scaling, power-efficient design will
inextricably be
linked with reliability concerns. Shipped hardware
will be vulnerable to
many power-related sources of faults (e.g., high temperature
exacerbates
wear-out). On the other hand, traditional reliability
solutions are
often power-hungry (e.g., redundancy). System designers
will therefore
need to optimize performance, reliability, and power
together. Further,
the best solutions will likely consider all system
layers together and
be customizable to the application. I will summarize
our recent efforts
in this area, and focus on a power-frugal, hardware-software
co-designed
reliability solution that treats hardware errors as
software bugs.
Bio:
Sarita Adve is Professor in Computer Science at the
University of
Illinois at Urbana-Champaign. Her research interests
are in computer
architecture and systems, with a current focus on power-efficient
and
reliable systems. She was named a UIUC University Scholar
in 2004 and
received an Alfred P. Sloan Research Fellowship in
1998, IBM
Faculty/Partnership Awards in 2005, 1998, and 1997,
and a National
Science Foundation CAREER award in 1995. She served
on the National
Science Foundation's CISE directorate's advisory committee
from 2003 to
2005 and on the expert group to revise the Java memory
model from 2001
to 2005. She received the Ph.D. in Computer Science
from the University
of Wisconsin - Madison in 1993.
Panel Session: "The
Problem of Increasing Variability and its Impact
on Power Consumption and System Design"
Panelists:
Sani Nassif, Manager, Tools and Technology, IBM Austin
Research Laboratory (Moderator)
Sarita Adve, Professor,
Dept. of Computer Science, University of Illinois
Urbana-Champaign
Shekhar Borkar, Intel
Fellow, Director, Intel Microprocessor Technology Lab
Joshua Friedrich, Microprocessor Designer, IBM Systems and Technology Group,
Austin
Vijaykrishna Narayanan,
Associate Professor, Computer Science and Engineering
Department., Pennsylvania State University
Tak Ning, IBM Fellow, TJ Watson Research Center Yorktown
Abstract:
Increasing system and circuit
densities have made power consumption one of the foremost
issues in computer system
design and management. Technology scaling, traditionally
a dominant lever driving computing performance growth
faces multiple impediments in lithography limitations,
increased leakage current, cooling density limitations,
and probably the
most important one of variability. Variability in device
and wire characteristics already impacts circuit performance
by changing delays,
but it also has an exponential impact on transistor leakage,
which causes large changes in the background (i.e. standby)
power of a circuit.
This increasing trend in leakage and its variability
is exacerbated with technology scaling, and has motivated
the introduction of sophisticated
circuit adaptation techniques to combat its impact. Panelists
will discuss the different sources of variability, debate
its impact on power
consumption and system design and potential solutions
to mitigate the problems arising from it.
Panelist Bios:
Josh Friedrich
Josh Friedrich was the circuit design lead for the
POWER6 memory subsystem. After the completion of the
1st pass design, he led the circuit characterization
of POWER6, optimizing both frequency and yield. On
past POWER processors, Josh has led the design of several
core units and been instrumental in power reduction
efforts. Josh is currently a chip power lead focusing
on power reduction efforts and energy efficiency.
