Michael Rosenfield
Director of IBM Austin Research Lab
Biography:
Michael Rosenfield is currently Director of the Austin
Research Lab focusing on high performance VLSI design and
tools, system level power analysis, and new system architectures.
His previous position was Senior Manager of VLSI Design and
Architecture at IBM T.J. Watson Research Center in Yorktown
Heights, NY where he and his team were involved in high performance
microprocessor VLSI design for IBM Server Group and Microelectronics,
tools, methodologies, and commonality as well as power-aware
microarchitecture, circuits/technology co-design, performance
analysis, exploratory microarchitectures, and advanced compiler
design. Previously, he has held management positions at Research
in parallel communication architecture and in advanced lithography.
In 1993, he was the technical assistant to the Research VP
of Systems, Technology, and Science. He has a Ph.D and M.S.
from the University of California, Berkeley and a B.S. in
Physics from the University of Vermont.
Keynote Speakers
Mark Papermaster
VP Technology Development IBM - Energy efficiency in computer
design topic
"The Challenge of Designing Cool Hot Chips"
Biography:
Mark Papermaster is the Vice President of Technology
Development for IBM Systems Group and is responsible for the
design and development of microprocessor, ASIC chip set, packaging,
and card technology. Mark has over 20 years of experience
in VLSI and microprocessor development, and his most recent
product responsibility included the design and development
of the POWER4, POWER5, and z990 mainframe processor families.
Mark completed his Bachelors of Science in Electrical Engineering
at the University of Texas in Austin in 1982, and Masters
of Science in Electrical Engineering at the University of
Vermont in 1986.
Dr. Raul Camposano
CTO Synopsys - Tools for energy efficient design topic
"What Can EDA Do For Energy Efficient Design? More
Than You Think..."
Abstract:
Pessimists state that within the next ten years or so, given
current trends, the maximal power density of approximately
100W/cm2 of today’s semiconductors will continue to
increase until they equal that of the surface of the sun.
Left unchecked, this means that roughly within two centuries,
our computational needs will consume the total energy (1059J)
available in our galaxy. Optimists, on the other hand, declare
that within the next few decades we will be able to forestall
such apolcalyptic energy predictions by making the transition
to nanotechnology. In either case, for contemporary designers,
one of the ultimate barriers to further scaling of CMOS is
the problem of power consumption.
System design provides a part of the answer to this challenge:
designers will increasingly use energy-efficient architectures,
control the degree of paralellism and necessary speed, turn
components on/off or adopt more energy efficient encoding
of values/states. Process technology also continues to improve
energy efficiency, e.g. by introducing lower resistance metal
(Cu), SoI, multiple gate structures, and multiple threshold
devices. In addition to these trends, EDA is crucial to enable
energy efficient design.
Analysis tools include full chip/block gate-level power analysis,
static and transient IR-drop and its impact on timing/power,
and EM analysis. Numerous implementation techniques are automated
in EDA tools and flows; the quadratic dependency of dynamic
power on voltage is exploited by multi-Vdd techniques such
as static voltage islands, dynamic voltage scaling and adaptive
voltage scaling. Clock, power, and data gating allow designers
to further reduce dynamic power consumption. Leakage power
is addressed by multi-Vth and power gating. Synthesis trades
power versus speed at the gate level, while physical design
can further influence power consumption in placement and clock-gating
implementation. In addition, the power grid needs to be designed
considering IR-drop and L dI/dt drop. This presentation will
show that not only does the combined use of the above techniques
increase the energy efficiency of a design by an order of
magnitude, but it also does it in an automated fashion that
is largely transparent to the designer.
Invited Speakers
Dr. Sandhya Dwarkadas
University of Rochester - HW/SW Integration topic
"An Integrated Hardware/Software Approach to On-Line
Power-Performance Optimization"
Abstract:
In order to reach the next level of performance and
energy efficiency,optimizations are increasingly being applied
in a dynamic and adaptive manner based on some measure of
an application's changing behavior. Our program behavior characterization
has shown that behavior variation can occur at several granularities,
from the micro to the macro scale, and that it can be predicted
with reasonable accuracy. The level at which these variations
are leveraged to maximize resource utilization (reducing energy
consumption while maintaining or improving performance) is
a function of the cost versus the benefit of the adaptation.
In this talk, I will present on-going work that explores
a whole-system view of on-line power-performance optimization
--- at the architecture, compiler, and operating system level
--- in the context of observed technology trends and both
single-threaded and multithreaded workloads.
Biography:
Sandhya Dwarkadas is an Associate Professor of Computer
Science and of Electrical and Computer Engineering at the
University of Rochester. She received her bachelor's degree
in Electrical and Electronics Engineering from the Indian
Institute of Technology, Madras, India, and her M.S. and Ph.D.
in Electrical and Computer Engineering from Rice University.
Her research interests span the interface of runtime systems,
compilers, and architecture, in the domain of parallel and
distributed systems as well as microarchitecture. She spent
the 2002-2003 academic year on sabbatical at IBM Watson focusing
on both microarchitectural and higher-level techniques to
leverage program behavior variability in improving performance
and energy efficiency.
Dr. Jonathan Koomey
Lawrence Berkeley Labs - Impact of energy efficiency topic
"Data center power use: a review of the historical
data"
Abstract:
This talk will describe the last few years of experience in
assessing the actual power densities in computer rooms and
related high density computing facilities. Initial reports
of 100-300 watts per square foot for computer rooms were in
conflict with measured data, which yielded total computer
room power densities (including HVAC and auxiliaries) of only
20-50 W/sf. This talk will describe the reasons for these
discrepancies, the latest measured data on power densities
from various case studies, and the likely future trends, given
the current oversupply of data center floor area in the US.
It will also summarize recent recommendations for improving
the efficiency of data
centers from the RMI Data Center Charrette and the LBNL case
studies, and describe the results of efficiency projects for
one data center facility that has been carefully documented
and tracked over the past few years.
Biography:
Jonathan G. Koomey, former leader of the End-Use Forecasting
Group, is now on leave as a staff scientist at Lawrence Berkeley
National Laboratory (his LBNL phone and email will still reach
him during this period, however). He holds the MAP/Ming visiting
professorship in energy and environment at Stanford University
for the 2003-2004 school year. Koomey has M.S. and Ph.D. degrees
from the Energy and Resources Group at the University of California
at Berkeley, and an A.B. (Cum Laude) in History of Science
from Harvard University. He is the author or co-author of
seven books and more than one hundred thirty articles and
reports on energy efficiency, climate change, and environmental
policy.
Koomey serves on the Editorial Board of the journal Contemporary
Economic Policy, and has appeared on Nova/Frontline, BBC Radio,
CNBC, and KQED radio. He has been quoted in the New York Times,
the Wall Street Journal, Barrons, the Washington Post, Science,
Science News, American Scientist, Dow Jones News Wires, USA
Today, and numerous other publications.
In 1993, his report Cost-Effectiveness of Fuel Economy Improvements
in 1992 Honda Civic Hatchbacks won the Fred Burgraff Award
for Excellence in Transportation Research from theNational
Research Council's Transportation Research Board.
http://enduse.lbl.gov/bios/jonathan.html
Dr. Kevin Skadron
University of Virginia - Power aware VLSI topic
"Challenges and Opportunities using Computer-Architecture
Techniques for Runtime Thermal Management"
Abstract:
In the first part of this talk I will describe why computer
architects can and should be playing a role in helping to
manage the growing problem of heat dissipation in microprocessors.
I will then briefly outline how temperature can be conveniently
simulated in conjunction with conventional architecture simulations,
and review and compare some techniques that have recently
been proposed for architectural thermal management, and discuss
the pros and cons of closed-loop feedback control.
In the second part of this talk I will discuss some of the
most important thermal modeling and design issues facing computer
architects. Among the most important are the implications
of different thermal time constants at different levels of
granularity, how to improve the precision of on-chip temperature
sensing, how to extend and integrate chip-level thermal management
with system-level thermal management, and how to better incorporate
reliability constraints into the design of thermal management.
Biography:
Kevin Skadron is an assistant professor in the Department
of Computer Science at the University of Virginia. He received
his PhD in Computer Science from Princeton University, and
bachelors' degrees in Electrical and Computer Engineering
as well as Economics from Rice University. At U.Va., he directs
the Laboratory for Computer Architecture at Virginia (LAVA),
studying power and thermal issues, branch prediction, and
techniques for fast and accurate microprocessor simulation.
Skadron's research group recently released "HotSpot",
a tool for dynamically modeling localized on-chip temperatures
in conjunction with architecture simulations; "HotLeakage",
a tool for dynamically modeling leakage energy in memory-like
structures, and "MRRL"; a tool for calculating the
minimum warmup period needed to avoid cold-start bias in sampled
simulation. Skadron will be program co-chair of the 2006 International
Conference on Parallel Architectures and Compilation Techniques
(PACT), general co-chair for the 2004 International Symposium
on Microarchitecture (MICRO), was general co-chair for PACT-2002,
and helped to launch Computer Architecture Letters, a new
short-format, refereed journal published by the IEEE Computer
Society TCCA.
Dr. Jason Flinn
University of Michigan - Power aware application topic
"Using Context to Improve Operating System Power
Management"
Abstract:
In this talk, I will describe how the operating system can
increase the battery lifetime of mobile computers by considering
additional context in its dynamic power management decisions.
Using wireless network power management as an example, I will
show that device-specific power management algorithms can
substantially degrade performance and even increase overall
energy usage for the computing system as a whole. I will then
discuss how the operating system can dynamically tune such
algorithms to the access patterns and intent of applications,
the characteristics of specific devices, and the power budget
of the mobile computer. Through consideration of this
additional context, the operating system can decrease total
energy usage for some applications by up to 21% while also
reducing network delays by 80%.
Next, I will discuss how the operating system can provide
additional interfaces that help coordinate power management
decisions. These interfaces enable applications, network interfaces,
and storage devices to collaborate to save energy. As a further
benefit, they provide a more intuitive way for users to control
power management.
Biography:
Jason Flinn is an assistant professor in the Electrical Engineering
and Computer Science department at the University of Michigan.
He received his PhD from Carnegie Mellon University in 2001.
His research interests include operating systems, mobile computing,
and dynamic power management.
Bruce Knaack
Director, Energy Efficiency Institute Program, IBM Austin
Research Laboratory
"IBM Activities in Energy Efficiency"
Abstract:
This talk is a discussion of the recently formed Energy Efficiency
Institute (EEI) within IBM. It's objectives and mission plus
some of the current activites sponsored by the EEI.
Biography:
Bruce Knaack is the low energy program manager for IBM research
group. He received an MS degree in computer science from the
University of Wisconsin. He has held a wide variety of positions
in IBM ranging from software architecture and development
thru product deployment and support.
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