| "Minimum Powered Thermal
Design for Portables"
Kazuaki Yazawa, Mobile Network Company, Sony Corporation,
Semiconductor Division, Sony Computer Entertainment
Inc.
ABSTRACT:
Since the design of consumer products is usually
limited by energy constraints, it is important to consider
a proper balance between power and functionality. This
presentation will start with a review of power consumption
trends of audio/video and information technology products.
Today, power management has a significant impact on
thermal design and it is getting more and more serious
due to the rapid growth of chip power consumption. Accordingly,
achieving high performance and low power is desired
even for thermal management. The highlight of this talk
will be the presentation of a thermal design method
that is both space and energy efficient for portable
electronics.
"Ultra-Low Power Computation and Communication
Enables Ambient Intelligence"
Dr. Jan M. Rabaey, University of California
at Berkeley
ABSTRACT:
An untapped opportunity in the realm of wireless data
lies in low data-rate low-cost wireless transceivers,
assembled into distributed networks of sensor and actuator
nodes. This enables applications such as smart buildings
and highways, environment monitoring, user interfaces,
entertainment, factory automation, and robotics. While
the aggregate system processes large amounts of data,
individual nodes participate in a small fraction only.
These ubiquitous networks require that the individual
nodes are tiny, easily integratable into the environment,
and have negligible cost. Most importantly, the nodes
must be self-contained in terms of energy via a one-time
battery charge or a replenishable supply of energy scavenged
from the environment. With the proposed size limitations,
battery power alone does not suffice to ensure self-containment.
Energy scavenging approaches can deliver up to 100 microWatt.
Achieving this ultra-low power-dissipation levels requires
reductions from the system architecture down to the
circuit technology. The presentation presents a number
of techniques to accomplish this with special emphasis
on the innovative circuit techniques.
"GSRC’s Power and Energy in Design
Research Activities"
Dr. Mary Jane Irwin, University of Penn State
ABSTRACT:
With no or little new technological miracle solutions
on the horizon for solving the looming power/energy
crisis, radical new design approaches and accompanying
design methodologies/tools are a necessity. Just as
with performance optimization, power optimization requires
careful design at several abstraction levels - from
innovative circuit fabrics, to the micro-architectures
that exploit them, to the software that runs on them
- and careful consideration of the interactions across
those levels. A sampling of the contributions in this
design space by the MARCO’s Gigascale Silicon Research
Center’s (GSRC) Power and Energy in Design (PED)
theme researchers will be presented ranging from:
- modeling novel circuit and interconnect fabrics
with respect to their active (dynamic) and standby
(leakage) power characteristics and quantifying their
impact on system performance and reliability,
- deriving new micro-architectural techniques for
improved power-delay-reliability outcomes that take
advantage of these novel circuit and interconnect
fabrics, and
- developing innovative software level optimizations
(e.g., compiler, run-time system, and application
codes) for improved power-delay-reliability outcomes
that exploit the features of these micro-architectures
for the applications running on them.
In support of these goals, theme members are in tandem
also developing validated power modeling tools at the
micro-architecture and system software levels, as well
as the fabrics level as mentioned above. Validated power-performance-reliability
models of the circuit fabrics are necessary tools for
the architect, as are validated micro-architecture simulators
for the software designer.
"Exploiting Application Phase Behavior to
Save Energy"
Dr. David Albonesi, University of Rochester
ABSTRACT:
In the course of execution, applications experience
phases that vary in their characteristics, and thus
their hardware requirements. We discuss two approaches
for exploiting this behavior for energy savings. We
first discuss the use of multiple adaptive structures
(issue queues, caches, and register files) to improve
energy efficiency without unduly compromising performance.
We then discuss the application of a globally-asynchronous,
locally-synchronous (GALS) design style to a dynamic
superscalar microprocessor, in which the processor is
divided into several independent clock domains. We discuss
the impact of synchronization on performance, and how
our use of fine-grain dynamic voltage scaling reduces
the energy of a broad class of applications.
Time-permitting, we will briefly present new front-end
policies for SMT processors that reduce required issue
queue resources, as well as our recent work on reducing
leakage in functional units.
"Dynamic
Power Management for Embedded Systems"
Hollis Blanchard, Bishop Brock, Matthew
Locke, Mark Orvek, Robert Paulsen, Karthick Rajamani
"Fine-Grained Clock-Gating with Interlocked
Synchronous Pipelining Techniques"
Hans Jacobson, Prabhakar Kudva, Pradip Bose, Peter Cook,
Stanley Schuster
"Energy Recovering Computers"
Conrad H. Ziesler, Joohee Kim, Dr. Marios C. Papaefthymiou,(University
of Michigan, Ann Arbor) and Suhwan Kim (IBM T.J. Watson
Research Center) |
