Turandot

Turandot is the superscalar processor model for the PowerPC architecture. This model is extensively parameterized, so that the same model can address numerous microarchitecture features. A typical configuration consists of components found in contemporary microprocessors but with their size and number increased to support wider instruction issue. The model implements a conventional pipeline but with variable number of stages to enable the effects of longer or shorter pipelines to be explored. For example, the pipeline's decode portion can range from one to four stages. Execution latencies vary depending on operation type; memory and floating-point operations require more stages than integer operations. Turandot models additional cycles for data cache misses and long-latency operations, such as divide and square-root.

The processor model lets designers explore multiple policies for removing operations from the issue queues and issuing them for execution. Policies commonly used include:

• An out-of-order policy issues each operation for execution as soon as the required operands and functional units are available, regardless of the order in which the operations were inserted in the issue queues. The issue logic selects the oldest one whenever multiple operations are ready for execution.
• A class-order policy issues the operations belonging to the same class of functional unit in program order, but allows out-of-order issuing among operations belonging to different classes.
• An in-order policy issues the operations in strict program order.

• instruction prefetching from a second level (L2) cache;
• decomposition of complex PowerPC instructions (such as load/store multiple or string operations) into multiple primitive operations;
• two-level translation look-aside buffer;
• clustering of functional units;
• L1/L2 cache bus features such as trailing-edge effects, multicycle transfers, critical-word first transfers;
• modeling of mispredicted instructions or stalling the pipeline until a mispredicted branch is resolved;
• dynamic load-over-store speculation with alias detection and recovery;
• various branch prediction algorithms for predicting branch direction/target.

Turandot also includes a mechanism to understand the behavior of a processor from the perspective of instruction retirement. Whenever an instruction cannot be retired in a given cycle, the cause ("trauma") that lead to such retirement failure is recorded. Histograms of traumas are provided at the end of a simulation session, which allow identifying the sources of performance degradation.

Turandot is the preferred processor modeling within The MET. Turandot takes advantage of the execution-driven features in Aria, but it can also processed instruction execution traces generated outside The MET.

See the Publications and Presentations for further information regarding Turandot.