Publications

	M. Moudgill, J-D. Wellman, J. Moreno, "Environment for PowerPC Microarchitecture Exploration," IEEE MICRO, May/June 1999, pp. 15-25. This paper describes The MET environment; it is an overview of the entire toolset, its functionality, and its implementation. It also includes some examples of microarchitecture exploration performed using the environment.
	M. Moudgill, P. Bose, J. Moreno, "Validation of Turandot, a Fast Processor Model for Microarchitecture Exploration," Proc. IEEE Int'l Performance, Computing and Communications Conference, February 1999, pp.452-457. This paper describes results in validating the performance projections from Turandot, the parameterized trace-driven simulation model of a speculative out-of-order superscalar processor. The paper summarizes the validation methodology used, and presents experimental data gathered on the calibration of one processor organization against a detailed reference model. The results indicate that, on the average for SPECint95 sampled traces, the processor model is within 5% of the results reported by the reference model, while exhibiting a speed-up factor of about 70.
	M. Moudgill, J-D. Wellman, J. Moreno, "An Approach for Quantifying the Impact of not Simulating Mispredicted Paths," Workshop on Performance Analysis and its Impact on Design (PAID), Barcelona, Spain, 1998. This paper describes an approach using Turandot and Aria for quantifying the potential error introduced by not simulating instructions from mispredicted paths in out-of-order speculative superscalar processors.
	J. Moreno, M. Moudgill, J-D. Wellman, P. Bose, L. Trevillyan, "Trace-driven Performance Exploration of a PowerPC 601 OLTP Workload on Wide Superscalar Processors," IBM Research Report RC20692, June 1997. This report describes the performance exploration on a PowerPC 601 execution trace from the TPC-C benchmark. This includes the evaluation of instruction-level parallelism as a function of issuing policy, processor width, size of caches, branch prediction accuracy. Performance factors are identified from the perspective of instruction retirement. The sensitivity to selected microarchitecture features is also studied.
	M. Moudgill, "An Overview of the LeProf Profiling Tool," IBM Research Report RC21169, April 1998. This report provides an overview of LeProf and LeProfT, and their use. The appendix also contains a detailed description of the output format from these tools.
	M. Moudgill, "Techniques for Implementing Fast Processor Simulators," Proc. IEEE 31st Annual Simulation Symposium, April 1998, pp. 83-90. Also available as IBM Research Report RC21175. This report describes the techniques that enable Turandot to execute over 350 million instructions per hour.
	M. Moudgill "Techniques for Fast Simulation of Associative Cache Directories," ACM Computer Architecture News, Vol. 26, No. 2, May 1998, pp. 1-8. Also available as IBM Research Report RC21038. This report describes in detail a new technique for efficient simulation of associative cache directories. This is one of the techniques used in Turandot that enable its high simulation performance.
	P. Bose, "Testing for Function and Performance: Towards an Integrated Processor Validation Methodology," Journal of Electronic Testing, Vol. 16, No. 1-2, February 2000.
	P. Bose, J.A. Abraham, "Performance and Functional Verification of Microprocessors," Proc. 13th IEEE International Conference on VLSI Design, January 2000.
	P. Bose, "Performance Test Case Generation for Microprocessors," Proc. 16th IEEE VLSI Test Symposium, April 1998, pp. 54-59. Also available as IBM Research Report RC21052.
	P. Bose et al., "Bounds-Based Loop Performance Analysis: Application to Validation and Tuning," Proc. IEEE Int'l Performance, Computing and Communications Conference, February 1998, pp. 178-184.