The device simulation features of DAMOCLES include the ability to define simple circuit boundary conditions. This means one or more independent device cross sections can be defined, and then the contacts of these device(s) can be connected to simple circuit networks consisting of ideal switches, resistors, capacitors, inductors, current sources or voltage sources. In addition, two or more contacts can be connected together with an "ideal" wire (no resistance, capacitance or inductance). Because all device cross sections are two-dimensional, this circuit boundary condition feature must also include a means to scale currents flowing from one device into another. This is necessary, for example, when wiring together two MOSFETs that have different physical channel widths (the direction perpendicular to the 2D simulation plane). This makes it possible to simulate a CMOS inverter where the ratio of p-MOSFET width to n-MOSFET width is not unity, as is the case in the example we now describe.

DAMOCLES has been used to simulate the transient response of a three stage CMOS inverter chain. A circuit schematic of a three stage inverter chain looks like this:

The individual n- and p-MOSFETs used in the inverter chain have been described previously in Y. Taur, C.H. Wann and D.J. Frank, "25 nm CMOS Design Considerations", Proceedings, 1998 IEDM, p. 789-792, 1998. The device metallurgical channel lengths are 19 nm; the gate lengths are 35 nm. The oxides are 1.5 nm thick. The power supply voltage $V$_DD = 1.0 V. The device doping profiles are dubbed "super-halo" by Taur, et al., and are described in the IEDM reference. Besides the intrinsic MOSFET devices and the input ramp and output load capacitor shown above, some parasitic circuit elements were added to each inverter to improve the realism of the modeling. The source leads of both the n- and p-MOSFETs have series conductances of 200 S/cm. The first and second stage outputs drive a fixed capacitive load of 0.1 pF/cm, in addition to the input of the next stage, to approximate wiring capacitance. The ratio of p-MOSFET width to n-MOSFET width is 2. Note a voltage vs. time response is included in the IEDM reference above; however, the simulations shown here supercede those results, which are somewhat slower in rise and fall time. The inverter chain simulation results are provided courtesy D.J. Frank.

Computer animations are provided to illustrate the internal device behaviors during a switching transient. Five animations of the second stage n- and p-MOSFET show how an inverter responds to a falling input voltage: the n-MOSFET turns off as the switching proceeds, while the p-MOSFET turns on and supplies the load capacitor with charge to change the output state of the inverter. Five animations of the third stage n- and p-MOSFET show how an inverter responds to a rising input voltage: the p-MOSFET turns off as the switching proceeds, while the n-MOSFET turns on and discharges the capacitive load. The five animations for both the second and third inverter stages consist of the following:

1. electron and hole particle kinetic energies, displayed in the 2D n- and p-MOSFET cross sections, respectively, as a function of time.
2. electron and hole carrier densities, displayed in the 2D n- and p-MOSFET cross sections, respectively, as a function of time.
3. electric field magnitude, displayed in the 2D n- and p-MOSFET cross sections, as a function of time.
4. electrostatic potential energy, displayed in the 2D n- and p-MOSFET cross sections, as a function of time.
5. total particle energy vs. position along the Si-SiO$$₂ interface, displayed in the n- and p-MOSFETs, as a function of time.

To access an animation, click on the image of a frame from the animation shown below. Each animation is 320x240 pixels in size, and depicts a total of 20 psec of switching operation. The first animation for a given stage runs for 32 seconds, while the remaining four run for 23 seconds. This is because the first animation contains additional introductory frames which pertain to each of the five animations. In fact, the five animations for a given stage are meant to be viewed end-to-end, in sequence, and were separated only for downloading convenience. These animations were shown at the 1999 Solid State Devices and Materials conference, held in Tokyo, Japan, as part of the invited talk "Full Band Monte Carlo Simulation of Small MOSFETs", by S.E. Laux and M.V. Fischetti.

Note: if you are having trouble viewing these animations, see these comments.

Animations of the second stage of the CMOS inverter chain:

Second stage particle kinetic energies vs. time:

320×240 avi; 4.27 Meg; 32 sec

320×240 avi; 2.44 Meg; 23 sec

320×240 avi; 2.55 Meg; 23 sec

320×240 avi; 2.42 Meg; 23 sec

320×240 avi; 2.08 Meg; 23 sec

Animations of the third stage of the CMOS inverter chain:

Third stage particle kinetic energies vs. time:

320×240 avi; 4.37 Meg; 32 sec

320×240 avi; 2.59 Meg; 23 sec

320×240 avi; 2.69 Meg; 23 sec

320×240 avi; 2.57 Meg; 23 sec

320×240 avi; 2.23 Meg; 23 sec